diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td index 6fe747800b5ad..2d8a47c08a5d2 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td @@ -177,7 +177,8 @@ class CustomSiFiveVMACC funct6, RISCVVFormat opv, string opcodestr> } class CustomSiFiveVFNRCLIP funct6, RISCVVFormat opv, string opcodestr> - : VALUVF { + : VALUVF, + SchedBinaryMC<"WriteSF_VFNRClipV", "ReadSF_VFNRClipV", "ReadSF_VFNRClipF"> { let Inst{6-0} = OPC_CUSTOM_2.Value; } @@ -403,7 +404,10 @@ multiclass VPseudoSiFiveVFNRCLIP { MxListVF4[i].vrclass, FPR32, MxListW[i], Constraint, /*sew*/0, - UsesVXRM=0>; + UsesVXRM=0>, + SchedBinary<"WriteSF_VFNRClipV", "ReadSF_VFNRClipV", + "ReadSF_VFNRClipF", + MxListW[i].MX>; } let Predicates = [HasVendorXSfvcp] in { diff --git a/llvm/lib/Target/RISCV/RISCVSchedAndes45.td b/llvm/lib/Target/RISCV/RISCVSchedAndes45.td index f42b48a1d8b83..58e9dc9c8535d 100644 --- a/llvm/lib/Target/RISCV/RISCVSchedAndes45.td +++ b/llvm/lib/Target/RISCV/RISCVSchedAndes45.td @@ -331,6 +331,7 @@ defm : UnsupportedSchedQ; defm : UnsupportedSchedSFB; defm : UnsupportedSchedV; defm : UnsupportedSchedXsfvcp; +defm : UnsupportedSchedXSfvfnrclipxfqf; defm : UnsupportedSchedZabha; defm : UnsupportedSchedZbkb; defm : UnsupportedSchedZbkx; diff --git a/llvm/lib/Target/RISCV/RISCVSchedGenericOOO.td b/llvm/lib/Target/RISCV/RISCVSchedGenericOOO.td index 6dd973bc1e83f..27871cb9d9f51 100644 --- a/llvm/lib/Target/RISCV/RISCVSchedGenericOOO.td +++ b/llvm/lib/Target/RISCV/RISCVSchedGenericOOO.td @@ -498,4 +498,5 @@ defm : UnsupportedSchedZfaWithQ; defm : UnsupportedSchedZvk; defm : UnsupportedSchedSFB; defm : UnsupportedSchedXsfvcp; +defm : UnsupportedSchedXSfvfnrclipxfqf; } diff --git a/llvm/lib/Target/RISCV/RISCVSchedMIPSP8700.td b/llvm/lib/Target/RISCV/RISCVSchedMIPSP8700.td index 8ba4cd0acdd6c..85b5886587de7 100644 --- a/llvm/lib/Target/RISCV/RISCVSchedMIPSP8700.td +++ b/llvm/lib/Target/RISCV/RISCVSchedMIPSP8700.td @@ -274,5 +274,6 @@ defm : UnsupportedSchedZfhmin; defm : UnsupportedSchedSFB; defm : UnsupportedSchedZabha; defm : UnsupportedSchedXsfvcp; +defm : UnsupportedSchedXSfvfnrclipxfqf; defm : UnsupportedSchedZvk; } diff --git a/llvm/lib/Target/RISCV/RISCVSchedRocket.td b/llvm/lib/Target/RISCV/RISCVSchedRocket.td index 4c4654ba2fc0f..1db0922bf2c5d 100644 --- a/llvm/lib/Target/RISCV/RISCVSchedRocket.td +++ b/llvm/lib/Target/RISCV/RISCVSchedRocket.td @@ -263,5 +263,6 @@ defm : UnsupportedSchedZfa; defm : UnsupportedSchedZfhmin; defm : UnsupportedSchedSFB; defm : UnsupportedSchedXsfvcp; +defm : UnsupportedSchedXSfvfnrclipxfqf; defm : UnsupportedSchedZvk; } diff --git a/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td b/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td index 6600a00d4e098..26964d070e67c 100644 --- a/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td +++ b/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td @@ -169,6 +169,20 @@ class SiFive7GetOrderedReductionCycles { int c = !mul(6, VLUpperBound); } +class SiFive7GetSiFiveVFNRClipCycles { + int latency = !cond( + !eq(mx, "MF8"): 7, + !eq(mx, "MF4"): 8, + !eq(mx, "MF2"): 10, + !eq(mx, "M1"): 13, + !eq(mx, "M2"): 19, + ); + + defvar DLEN = !div(VLEN, 2); + int occupancy = SiFive7GetCyclesOnePerElement.c; +} + class SiFive7FPLatencies { int BasicFP16ALU; int BasicFP32ALU; @@ -1049,6 +1063,15 @@ multiclass SiFive7WriteResBase; + let Latency = Cycles.latency, + AcquireAtCycles = [0, 1], + ReleaseAtCycles = [1, !add(1, Cycles.occupancy)] in + defm : LMULWriteResMX<"WriteSF_VFNRClipV", [VCQ, VA1], mx, + IsWorstCase=!eq(mx, "M2")>; + } } //===----------------------------------------------------------------------===// @@ -1326,6 +1349,10 @@ multiclass SiFive7ReadAdvance { def : ReadAdvance; def : ReadAdvance; + // XSfvfnrclipxfqf + defm : LMULReadAdvance<"ReadSF_VFNRClipV", 0>; + defm : LMULReadAdvance<"ReadSF_VFNRClipF", 0>; + // Others def : ReadAdvance; def : ReadAdvance; diff --git a/llvm/lib/Target/RISCV/RISCVSchedSiFiveP400.td b/llvm/lib/Target/RISCV/RISCVSchedSiFiveP400.td index 370ea64699383..e542d0e2301d0 100644 --- a/llvm/lib/Target/RISCV/RISCVSchedSiFiveP400.td +++ b/llvm/lib/Target/RISCV/RISCVSchedSiFiveP400.td @@ -1239,4 +1239,5 @@ defm : UnsupportedSchedZbkx; defm : UnsupportedSchedSFB; defm : UnsupportedSchedZfa; defm : UnsupportedSchedXsfvcp; +defm : UnsupportedSchedXSfvfnrclipxfqf; } diff --git a/llvm/lib/Target/RISCV/RISCVSchedSiFiveP500.td b/llvm/lib/Target/RISCV/RISCVSchedSiFiveP500.td index 5933d73174f79..184773f943bb1 100644 --- a/llvm/lib/Target/RISCV/RISCVSchedSiFiveP500.td +++ b/llvm/lib/Target/RISCV/RISCVSchedSiFiveP500.td @@ -359,4 +359,5 @@ defm : UnsupportedSchedSFB; defm : UnsupportedSchedZfa; defm : UnsupportedSchedZvk; defm : UnsupportedSchedXsfvcp; +defm : UnsupportedSchedXSfvfnrclipxfqf; } diff --git a/llvm/lib/Target/RISCV/RISCVSchedSiFiveP600.td b/llvm/lib/Target/RISCV/RISCVSchedSiFiveP600.td index 7c04d1c54473d..535c639c3150f 100644 --- a/llvm/lib/Target/RISCV/RISCVSchedSiFiveP600.td +++ b/llvm/lib/Target/RISCV/RISCVSchedSiFiveP600.td @@ -1495,4 +1495,5 @@ defm : UnsupportedSchedZbkx; defm : UnsupportedSchedSFB; defm : UnsupportedSchedZfa; defm : UnsupportedSchedXsfvcp; +defm : UnsupportedSchedXSfvfnrclipxfqf; } diff --git a/llvm/lib/Target/RISCV/RISCVSchedSiFiveP800.td b/llvm/lib/Target/RISCV/RISCVSchedSiFiveP800.td index f2b660583f27f..0bd73a0b80163 100644 --- a/llvm/lib/Target/RISCV/RISCVSchedSiFiveP800.td +++ b/llvm/lib/Target/RISCV/RISCVSchedSiFiveP800.td @@ -1184,4 +1184,5 @@ defm : UnsupportedSchedZbkx; defm : UnsupportedSchedSFB; defm : UnsupportedSchedZfaWithQ; defm : UnsupportedSchedXsfvcp; +defm : UnsupportedSchedXSfvfnrclipxfqf; } diff --git a/llvm/lib/Target/RISCV/RISCVSchedSpacemitX60.td b/llvm/lib/Target/RISCV/RISCVSchedSpacemitX60.td index 9059d5a4e497b..ea6e47260166c 100644 --- a/llvm/lib/Target/RISCV/RISCVSchedSpacemitX60.td +++ b/llvm/lib/Target/RISCV/RISCVSchedSpacemitX60.td @@ -346,6 +346,7 @@ def : ReadAdvance; defm : UnsupportedSchedQ; defm : UnsupportedSchedV; defm : UnsupportedSchedXsfvcp; +defm : UnsupportedSchedXSfvfnrclipxfqf; defm : UnsupportedSchedZabha; defm : UnsupportedSchedZbkb; defm : UnsupportedSchedZbkx; diff --git a/llvm/lib/Target/RISCV/RISCVSchedSyntacoreSCR1.td b/llvm/lib/Target/RISCV/RISCVSchedSyntacoreSCR1.td index 4aa74b020825c..18c463500b961 100644 --- a/llvm/lib/Target/RISCV/RISCVSchedSyntacoreSCR1.td +++ b/llvm/lib/Target/RISCV/RISCVSchedSyntacoreSCR1.td @@ -117,5 +117,6 @@ defm : UnsupportedSchedZbkb; defm : UnsupportedSchedZbkx; defm : UnsupportedSchedZfa; defm : UnsupportedSchedXsfvcp; +defm : UnsupportedSchedXSfvfnrclipxfqf; defm : UnsupportedSchedZvk; } diff --git a/llvm/lib/Target/RISCV/RISCVSchedSyntacoreSCR345.td b/llvm/lib/Target/RISCV/RISCVSchedSyntacoreSCR345.td index 815c2da992a11..6b3d6b24b8017 100644 --- a/llvm/lib/Target/RISCV/RISCVSchedSyntacoreSCR345.td +++ b/llvm/lib/Target/RISCV/RISCVSchedSyntacoreSCR345.td @@ -183,6 +183,7 @@ multiclass SCR_Unsupported : UnsupportedSchedSFB, UnsupportedSchedV, UnsupportedSchedXsfvcp, + UnsupportedSchedXSfvfnrclipxfqf, UnsupportedSchedZabha, UnsupportedSchedZba, UnsupportedSchedZbb, diff --git a/llvm/lib/Target/RISCV/RISCVSchedSyntacoreSCR7.td b/llvm/lib/Target/RISCV/RISCVSchedSyntacoreSCR7.td index decd578360753..ee25c961515c0 100644 --- a/llvm/lib/Target/RISCV/RISCVSchedSyntacoreSCR7.td +++ b/llvm/lib/Target/RISCV/RISCVSchedSyntacoreSCR7.td @@ -245,6 +245,7 @@ multiclass SCR7_Unsupported { defm : UnsupportedSchedSFB; defm : UnsupportedSchedV; defm : UnsupportedSchedXsfvcp; + defm : UnsupportedSchedXSfvfnrclipxfqf; defm : UnsupportedSchedZabha; defm : UnsupportedSchedZfa; defm : UnsupportedSchedZfhmin; diff --git a/llvm/lib/Target/RISCV/RISCVSchedTTAscalonD8.td b/llvm/lib/Target/RISCV/RISCVSchedTTAscalonD8.td index 5322de100d0ad..d4f0d904b8e89 100644 --- a/llvm/lib/Target/RISCV/RISCVSchedTTAscalonD8.td +++ b/llvm/lib/Target/RISCV/RISCVSchedTTAscalonD8.td @@ -321,6 +321,7 @@ def : ReadAdvance; defm : UnsupportedSchedQ; defm : UnsupportedSchedV; defm : UnsupportedSchedXsfvcp; +defm : UnsupportedSchedXSfvfnrclipxfqf; defm : UnsupportedSchedZabha; defm : UnsupportedSchedZbc; defm : UnsupportedSchedZbkb; diff --git a/llvm/lib/Target/RISCV/RISCVSchedXiangShanNanHu.td b/llvm/lib/Target/RISCV/RISCVSchedXiangShanNanHu.td index 3076a2ebb813d..735316e48745d 100644 --- a/llvm/lib/Target/RISCV/RISCVSchedXiangShanNanHu.td +++ b/llvm/lib/Target/RISCV/RISCVSchedXiangShanNanHu.td @@ -313,5 +313,6 @@ defm : UnsupportedSchedZfhmin; defm : UnsupportedSchedSFB; defm : UnsupportedSchedZabha; defm : UnsupportedSchedXsfvcp; +defm : UnsupportedSchedXSfvfnrclipxfqf; defm : UnsupportedSchedZvk; } diff --git a/llvm/lib/Target/RISCV/RISCVScheduleXSf.td b/llvm/lib/Target/RISCV/RISCVScheduleXSf.td index 58d508460f019..56be7a1308a1c 100644 --- a/llvm/lib/Target/RISCV/RISCVScheduleXSf.td +++ b/llvm/lib/Target/RISCV/RISCVScheduleXSf.td @@ -57,3 +57,15 @@ foreach f = ["FPR16", "FPR32", "FPR64"] in { } } } + +defm "" : LMULSchedWritesImpl<"WriteSF_VFNRClipV", !listremove(SchedMxListW, ["M4"])>; +defm "" : LMULSchedReadsImpl<"ReadSF_VFNRClipV", !listremove(SchedMxListW, ["M4"])>; +defm "" : LMULSchedReadsImpl<"ReadSF_VFNRClipF", !listremove(SchedMxListW, ["M4"])>; + +multiclass UnsupportedSchedXSfvfnrclipxfqf { +let Unsupported = true in { +defm : LMULWriteRes<"WriteSF_VFNRClipV", []>; +defm : LMULReadAdvance<"ReadSF_VFNRClipV", 0>; +defm : LMULReadAdvance<"ReadSF_VFNRClipF", 0>; +} // Unsupported = true +} diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFive7/xsfvfnrclip.s b/llvm/test/tools/llvm-mca/RISCV/SiFive7/xsfvfnrclip.s new file mode 100644 index 0000000000000..a9499edceda35 --- /dev/null +++ b/llvm/test/tools/llvm-mca/RISCV/SiFive7/xsfvfnrclip.s @@ -0,0 +1,79 @@ +# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py +# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-x280 -mattr='+xsfvfnrclipxfqf' -iterations=1 -instruction-tables=full %s | \ +# RUN: FileCheck %s + +vsetvli a0, zero, e8, mf8, ta, ma +sf.vfnrclip.xu.f.qf v4, v8, fa2 + +vsetvli a0, zero, e8, mf4, ta, ma +sf.vfnrclip.xu.f.qf v4, v8, fa2 + +vsetvli a0, zero, e8, mf2, ta, ma +sf.vfnrclip.xu.f.qf v4, v8, fa2 + +vsetvli a0, zero, e8, m1, ta, ma +sf.vfnrclip.xu.f.qf v4, v8, fa2 + +vsetvli a0, zero, e8, m2, ta, ma +sf.vfnrclip.xu.f.qf v4, v8, fa2 + +# CHECK: Resources: +# CHECK-NEXT: [0] - VLEN512SiFive7FDiv:1 +# CHECK-NEXT: [1] - VLEN512SiFive7IDiv:1 +# CHECK-NEXT: [2] - VLEN512SiFive7PipeA:1 +# CHECK-NEXT: [3] - VLEN512SiFive7PipeAB:2 VLEN512SiFive7PipeA, VLEN512SiFive7PipeB +# CHECK-NEXT: [4] - VLEN512SiFive7PipeB:1 +# CHECK-NEXT: [5] - VLEN512SiFive7VA:1 +# CHECK-NEXT: [6] - VLEN512SiFive7VCQ:1 +# CHECK-NEXT: [7] - VLEN512SiFive7VL:1 +# CHECK-NEXT: [8] - VLEN512SiFive7VS:1 + +# CHECK: Instruction Info: +# CHECK-NEXT: [1]: #uOps +# CHECK-NEXT: [2]: Latency +# CHECK-NEXT: [3]: RThroughput +# CHECK-NEXT: [4]: MayLoad +# CHECK-NEXT: [5]: MayStore +# CHECK-NEXT: [6]: HasSideEffects (U) +# CHECK-NEXT: [7]: Bypass Latency +# CHECK-NEXT: [8]: Resources ( | [] | [, | [] | [,