Search results

[TargetLowering] Change getOptimalMemOpType and findOptimalMemOpLowering to take LLVM Context

backend:AArch64

backend:AMDGPU

backend:ARM

backend:Hexagon

backend:MIPS

backend:PowerPC

backend:RISC-V

backend:SystemZ

backend:X86

llvm:SelectionDAGSelectionDAGISel as wellSelectionDAGISel as well

Status: Open (in progress).

llvm/llvm-projectnumber 147664

#147664 In llvm/llvm-project;

· BoyaoWang430 opened on Jul 9, 2025

[RISCV] Optimize (and (icmp x, 0, eq), (icmp y, 0, eq)) utilizing zicond extension

backend:AArch64

backend:RISC-V

llvm:SelectionDAGSelectionDAGISel as wellSelectionDAGISel as well

Status: Open (in progress).

llvm/llvm-projectnumber 147627

#147627 In llvm/llvm-project;

· bababuck opened on Jul 9, 2025

MachineLICM: Merge logic for implicit and explicit definitions.

backend:AArch64

backend:AMDGPU

backend:RISC-V

backend:X86

llvm:codegen

Status: Open (in progress).

llvm/llvm-projectnumber 147624

#147624 In llvm/llvm-project;

· pcc opened on Jul 9, 2025

[FMV][AArch64] Convert user facing priority syntax to internal.

backend:AArch64

clangClang issues not falling into any other categoryClang issues not falling into any other category

clang:codegenIR generation bugs: mangling, exceptions, etc.IR generation bugs: mangling, exceptions, etc.

clang:frontendLanguage frontend issues, e.g. anything involving "Sema"Language frontend issues, e.g. anything involving "Sema"

llvm:analysisIncludes value tracking, cost tables and constant foldingIncludes value tracking, cost tables and constant folding

llvm:transforms

Status: Draft (not ready).

llvm/llvm-projectnumber 147607

#147607 In llvm/llvm-project;

· labrinea opened on Jul 8, 2025

[LoopStrengthReduce] Mitigation of issues introduced by compilation time optimization in SolveRecurse.

backend:AArch64

backend:AMDGPU

backend:ARM

backend:NVPTX

backend:PowerPC

backend:RISC-V

backend:WebAssembly

backend:X86

llvm:transforms

Status: Open (in progress).

llvm/llvm-projectnumber 147588

#147588 In llvm/llvm-project;

· SergeyShch01 opened on Jul 8, 2025

[IA] Support deinterleave intrinsics w/ fewer than N extracts

backend:AArch64

backend:RISC-V

llvm:codegen

Status: Open (in progress).

llvm/llvm-projectnumber 147572

#147572 In llvm/llvm-project;

· preames opened on Jul 8, 2025

[AArch64][SVE] Avoid using the SVE stack size before it is determined (hopefully mostly a NFC)

backend:AArch64

debuginfo

Status: Open (in progress).

llvm/llvm-projectnumber 147561

#147561 In llvm/llvm-project;

· MacDue opened on Jul 8, 2025

[AArch64] Use SVE2 bit-sel instructions for some binary patterns.

backend:AArch64

Status: Open (in progress).

llvm/llvm-projectnumber 147544

#147544 In llvm/llvm-project;

· rj-jesus opened on Jul 8, 2025

[LLVM][CodeGen][SVE] Make bf16 fabs/fneg isel consistent with fp16.

backend:AArch64

Status: Open (in progress).

llvm/llvm-projectnumber 147543

#147543 In llvm/llvm-project;

· paulwalker-arm opened on Jul 8, 2025

[LoopVectorize] Generate wide active lane masks

backend:AArch64

llvm:analysisIncludes value tracking, cost tables and constant foldingIncludes value tracking, cost tables and constant folding

llvm:transforms

vectorizers

Status: Open (in progress).

llvm/llvm-projectnumber 147535

#147535 In llvm/llvm-project;

· kmclaughlin-arm opened on Jul 8, 2025

[GlobalISel] Add Saturated Truncate Instructions

backend:AArch64

llvm:codegen

llvm:globalisel

llvm:support

mcMachine (object) codeMachine (object) code

Status: Open (in progress).

llvm/llvm-projectnumber 147526

#147526 In llvm/llvm-project;

· jyli0116 opened on Jul 8, 2025

[AArch64] Use mov imm pseudo instructions in madd combine.

backend:AArch64

Status: Open (in progress).

llvm/llvm-projectnumber 147510

#147510 In llvm/llvm-project;

· davemgreen opened on Jul 8, 2025