LLVM MCA claims Skylake can issue 6 instructions per clock

[SeeSpring]

.att_syntax
.loop:
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	incq	%rax
	cmpq	$999, %rax
	jne	.loop

Godbolt

UICA predicts 4.50 cycles per iteration due to an issue bottleneck; MCA claims 3.2

According to Agner,

The maximum throughput from the decoders is four instructions or five μops per clock cycle

Similar problem with Icelake, again from Agner

The maximum throughput is improved to five instructions per clock cycle, where Skylake has four.

[topperc]

Maybe it's counting the Decode Stream Buffer?

From Intel Optimization Manual

The DSB delivers 6 uops per cycle to the IDQ compared to 4 uops in previous generations.

[SeeSpring]

I think UICA agrees with the 6 wide DSB to IDQ, but MCA doesn't model the bottleneck on issuing instruction from the IDQ.
Additionally, Intel Optimization manual 2.4.1 ICE LAKE CLIENT MICROARCHITECTURE OVERVIEW says

Wider machine: 4 -> 5 wide allocation, 8 -> 10 execution ports.

which implies Skylake is 4 wide and Icelake is 5 wide

[SeeSpring]

Additionally I noticed

llvm-project/llvm/lib/Target/X86/X86SchedSkylakeClient.td

Lines 15 to 17 in a8c3b3e

	// All x86 instructions are modeled as a single micro-op, and SKylake can
	// decode 6 instructions per cycle.
	let IssueWidth = 6;

claiming that Skylake can decode 6 instructions per cycle, but Intel Optimization Manual 2.6.1 SKYLAKE CLIENT MICROARCHITECTURE THE FRONT END says

Legacy Decode Pipeline delivery of 5 uops per cycle to the IDQ compared to 4 uops in previous generations.

And Agner 11.2 Intel Skylake pipeline Instruction fetch and decoding says

The maximum throughput from the decoders is four instructions or five μops per clock cycle.

Assuming all x86 instructions are single uop, Skylake can only decode 4 per cycle. (But this is about issue width, not decode width)

[llvmbot]

@llvm/issue-subscribers-backend-x86

Author: None (SeeSpring)

``` .att_syntax .loop: nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop incq %rax cmpq $999, %rax jne .loop ``` [Godbolt](https://godbolt.org/#z:OYLghAFBqd5QCxAYwPYBMCmBRdBLAF1QCcAaPECAMzwBtMA7AQwFtMQByARg9KtQYEAysib0QXACx8BBAKoBnTAAUAHpwAMvAFYTStJg1CGxATwV4FpJfWQE8Ayo3QBhVLQCuLBnucAZPAZMADkvACNMYj0AB1QLewE3T28YuMIHBgCg0JYIqK5rTFsEhiECJmICJK8fAptMOwyyioIskPDIvQVyyuqUup7WwPbczq4ASmtUD2Jkdg4AOiYCAgB9BVNBJlUAUg0AQQXaVFRokD39vYBOBlOL69vo%2B40bu4OHt8uXx%2BfXp/fvp8Pv8vn9fj8AWDIRDQTDgeCgYCQddAsgAI7XHYAJgArMRtr9kCxohiXgASK6U0gAamxeIJkO0QWuRxO0Q4k1onBxvB8HC0pFQnH2zFo5ks1IU01mmFpWIAzDxSARNBzJgBrEA4jT6TiSXmqwWcXgKEA6lX8jmkOCwJBoYl0SLkSj26KOqK0WgANxYAFoWKICMQPAx1Xw6ARIqaIGFDWFAhVTJwlfHmMRTAB5MLaBoWpX2tiCDMMMWGrBhDzAFxiWim7i8LAsQzAcSW0j4Yi5vBezB1gWYVQNDyR5O8QKRrlt2h4ML49NuLCGoN4FijyZUAzABQANTwmAA7hnooxRzJBCIxOwpGf5Eo1IbdAUDEYQCYxRYrNOwqbIJNTiU639ZBog8HZ5QAEQUdVTAMdVMF4VAe2IYg8CwH8IEmepGkcCBnD6WpSH8YYcjyVJ4gyfCyPSAQ2hIsZCmKJpBkouoii7ARmkqWiOnyaxmPcGoukGbjRnyTDpTmCROW5A02yFDhqU9H0gKYakICDEN1XGNTcEIEg5UVcZeAtLRxg1LUdUnfVSFXLgNB1PkBXkk0zWVVUzN1DgsVkpzjTcy0PKQixHEkIA)

UICA predicts 4.50 cycles per iteration due to an issue bottleneck; MCA claims 3.2

According to Agner,
> The maximum throughput from the decoders is four instructions or five μops per clock cycle

Similar problem with Icelake, again from Agner
> The maximum throughput is improved to five instructions per clock cycle, where Skylake has four.