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[MLIR] Make the ROCM integration tests runnable
- Move the #define s to the GPU Transform library from GPU Ops so that SerializeToHsaco is non-trivially compiled - Add required includes to SerializeToHsaco - Move MCSubtargetInfo creation to the correct point in the compilation process - Change mlir in ROCM tests to account for renamed/moved ops Differential Revision: https://reviews.llvm.org/D114184
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7 files changed

+50
-41
lines changed

7 files changed

+50
-41
lines changed

‎mlir/lib/Dialect/GPU/CMakeLists.txt

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -145,14 +145,14 @@ if(MLIR_ENABLE_ROCM_RUNNER)
145145
message(STATUS "ROCm HIP version: ${HIP_VERSION}")
146146
endif()
147147

148-
target_compile_definitions(obj.MLIRGPUOps
148+
target_compile_definitions(obj.MLIRGPUTransforms
149149
PRIVATE
150150
__HIP_PLATFORM_HCC__
151151
__ROCM_PATH__="${ROCM_PATH}"
152152
MLIR_GPU_TO_HSACO_PASS_ENABLE=1
153153
)
154154

155-
target_include_directories(obj.MLIRGPUOps
155+
target_include_directories(obj.MLIRGPUTransforms
156156
PRIVATE
157157
${MLIR_SOURCE_DIR}/../lld/include
158158
${HIP_PATH}/include

‎mlir/lib/Dialect/GPU/Transforms/SerializeToHsaco.cpp

Lines changed: 9 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -11,6 +11,8 @@
1111
//
1212
//===----------------------------------------------------------------------===//
1313
#include "mlir/Dialect/GPU/Passes.h"
14+
#include "mlir/IR/Location.h"
15+
#include "mlir/IR/MLIRContext.h"
1416

1517
#if MLIR_GPU_TO_HSACO_PASS_ENABLE
1618
#include "mlir/Pass/Pass.h"
@@ -32,8 +34,11 @@
3234
#include "llvm/Support/FileUtilities.h"
3335
#include "llvm/Support/LineIterator.h"
3436
#include "llvm/Support/Program.h"
37+
#include "llvm/Support/SourceMgr.h"
3538
#include "llvm/Support/TargetSelect.h"
3639
#include "llvm/Support/WithColor.h"
40+
41+
#include "llvm/Target/TargetMachine.h"
3742
#include "llvm/Target/TargetOptions.h"
3843

3944
#include "lld/Common/Driver.h"
@@ -170,8 +175,11 @@ SerializeToHsacoPass::assembleIsa(const std::string &isa) {
170175
std::unique_ptr<llvm::MCAsmInfo> mai(
171176
target->createMCAsmInfo(*mri, this->triple, mcOptions));
172177
mai->setRelaxELFRelocations(true);
178+
std::unique_ptr<llvm::MCSubtargetInfo> sti(
179+
target->createMCSubtargetInfo(this->triple, this->chip, this->features));
173180

174-
llvm::MCContext ctx(triple, mai.get(), mri.get(), &srcMgr, &mcOptions);
181+
llvm::MCContext ctx(triple, mai.get(), mri.get(), sti.get(), &srcMgr,
182+
&mcOptions);
175183
std::unique_ptr<llvm::MCObjectFileInfo> mofi(target->createMCObjectFileInfo(
176184
ctx, /*PIC=*/false, /*LargeCodeModel=*/false));
177185
ctx.setObjectFileInfo(mofi.get());
@@ -182,8 +190,6 @@ SerializeToHsacoPass::assembleIsa(const std::string &isa) {
182190

183191
std::unique_ptr<llvm::MCStreamer> mcStreamer;
184192
std::unique_ptr<llvm::MCInstrInfo> mcii(target->createMCInstrInfo());
185-
std::unique_ptr<llvm::MCSubtargetInfo> sti(
186-
target->createMCSubtargetInfo(this->triple, this->chip, this->features));
187193

188194
llvm::MCCodeEmitter *ce = target->createMCCodeEmitter(*mcii, *mri, ctx);
189195
llvm::MCAsmBackend *mab = target->createMCAsmBackend(*sti, *mri, mcOptions);

‎mlir/lib/ExecutionEngine/CMakeLists.txt

Lines changed: 4 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -202,8 +202,11 @@ if(MLIR_ENABLE_ROCM_RUNNER)
202202
${HIP_PATH}/include
203203
${ROCM_PATH}/include
204204
)
205+
set_property(TARGET mlir_rocm_runtime
206+
PROPERTY INSTALL_RPATH_USE_LINK_PATH ON)
207+
205208
target_link_libraries(mlir_rocm_runtime
206-
PRIVATE
209+
PUBLIC
207210
${ROCM_RUNTIME_LIBRARY}
208211
)
209212
endif()

‎mlir/test/Integration/GPU/ROCM/gpu-to-hsaco.mlir

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -11,23 +11,23 @@
1111
func @other_func(%arg0 : f32, %arg1 : memref<?xf32>) {
1212
%c0 = arith.constant 0 : index
1313
%c1 = arith.constant 1 : index
14-
%block_dim = dim %arg1, %c0 : memref<?xf32>
14+
%block_dim = memref.dim %arg1, %c0 : memref<?xf32>
1515
gpu.launch blocks(%bx, %by, %bz) in (%grid_x = %c1, %grid_y = %c1, %grid_z = %c1)
1616
threads(%tx, %ty, %tz) in (%block_x = %block_dim, %block_y = %c1, %block_z = %c1) {
17-
store %arg0, %arg1[%tx] : memref<?xf32>
17+
memref.store %arg0, %arg1[%tx] : memref<?xf32>
1818
gpu.terminator
1919
}
2020
return
2121
}
2222

2323
// CHECK: [1, 1, 1, 1, 1]
2424
func @main() {
25-
%arg0 = alloc() : memref<5xf32>
25+
%arg0 = memref.alloc() : memref<5xf32>
2626
%21 = arith.constant 5 : i32
27-
%22 = memref_cast %arg0 : memref<5xf32> to memref<?xf32>
28-
%cast = memref_cast %22 : memref<?xf32> to memref<*xf32>
27+
%22 = memref.cast %arg0 : memref<5xf32> to memref<?xf32>
28+
%cast = memref.cast %22 : memref<?xf32> to memref<*xf32>
2929
gpu.host_register %cast : memref<*xf32>
30-
%23 = memref_cast %22 : memref<?xf32> to memref<*xf32>
30+
%23 = memref.cast %22 : memref<?xf32> to memref<*xf32>
3131
call @print_memref_f32(%23) : (memref<*xf32>) -> ()
3232
%24 = arith.constant 1.0 : f32
3333
%25 = call @mgpuMemGetDeviceMemRef1dFloat(%22) : (memref<?xf32>) -> (memref<?xf32>)

‎mlir/test/Integration/GPU/ROCM/two-modules.mlir

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -10,24 +10,24 @@
1010

1111
// CHECK: [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12]
1212
func @main() {
13-
%arg = alloc() : memref<13xi32>
14-
%dst = memref_cast %arg : memref<13xi32> to memref<?xi32>
13+
%arg = memref.alloc() : memref<13xi32>
14+
%dst = memref.cast %arg : memref<13xi32> to memref<?xi32>
1515
%c0 = arith.constant 0 : index
1616
%c1 = arith.constant 1 : index
17-
%sx = dim %dst, %c0 : memref<?xi32>
18-
%cast_dst = memref_cast %dst : memref<?xi32> to memref<*xi32>
17+
%sx = memref.dim %dst, %c0 : memref<?xi32>
18+
%cast_dst = memref.cast %dst : memref<?xi32> to memref<*xi32>
1919
gpu.host_register %cast_dst : memref<*xi32>
2020
%dst_device = call @mgpuMemGetDeviceMemRef1dInt32(%dst) : (memref<?xi32>) -> (memref<?xi32>)
2121
gpu.launch blocks(%bx, %by, %bz) in (%grid_x = %c1, %grid_y = %c1, %grid_z = %c1)
2222
threads(%tx, %ty, %tz) in (%block_x = %sx, %block_y = %c1, %block_z = %c1) {
2323
%t0 = arith.index_cast %tx : index to i32
24-
store %t0, %dst_device[%tx] : memref<?xi32>
24+
memref.store %t0, %dst_device[%tx] : memref<?xi32>
2525
gpu.terminator
2626
}
2727
gpu.launch blocks(%bx, %by, %bz) in (%grid_x = %c1, %grid_y = %c1, %grid_z = %c1)
2828
threads(%tx, %ty, %tz) in (%block_x = %sx, %block_y = %c1, %block_z = %c1) {
2929
%t0 = arith.index_cast %tx : index to i32
30-
store %t0, %dst_device[%tx] : memref<?xi32>
30+
memref.store %t0, %dst_device[%tx] : memref<?xi32>
3131
gpu.terminator
3232
}
3333
call @print_memref_i32(%cast_dst) : (memref<*xi32>) -> ()

‎mlir/test/Integration/GPU/ROCM/vecadd.mlir

Lines changed: 15 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -12,13 +12,13 @@
1212
func @vecadd(%arg0 : memref<?xf32>, %arg1 : memref<?xf32>, %arg2 : memref<?xf32>) {
1313
%c0 = arith.constant 0 : index
1414
%c1 = arith.constant 1 : index
15-
%block_dim = dim %arg0, %c0 : memref<?xf32>
15+
%block_dim = memref.dim %arg0, %c0 : memref<?xf32>
1616
gpu.launch blocks(%bx, %by, %bz) in (%grid_x = %c1, %grid_y = %c1, %grid_z = %c1)
1717
threads(%tx, %ty, %tz) in (%block_x = %block_dim, %block_y = %c1, %block_z = %c1) {
18-
%a = load %arg0[%tx] : memref<?xf32>
19-
%b = load %arg1[%tx] : memref<?xf32>
18+
%a = memref.load %arg0[%tx] : memref<?xf32>
19+
%b = memref.load %arg1[%tx] : memref<?xf32>
2020
%c = arith.addf %a, %b : f32
21-
store %c, %arg2[%tx] : memref<?xf32>
21+
memref.store %c, %arg2[%tx] : memref<?xf32>
2222
gpu.terminator
2323
}
2424
return
@@ -30,19 +30,19 @@ func @main() {
3030
%c1 = arith.constant 1 : index
3131
%c5 = arith.constant 5 : index
3232
%cf1dot23 = arith.constant 1.23 : f32
33-
%0 = alloc() : memref<5xf32>
34-
%1 = alloc() : memref<5xf32>
35-
%2 = alloc() : memref<5xf32>
36-
%3 = memref_cast %0 : memref<5xf32> to memref<?xf32>
37-
%4 = memref_cast %1 : memref<5xf32> to memref<?xf32>
38-
%5 = memref_cast %2 : memref<5xf32> to memref<?xf32>
33+
%0 = memref.alloc() : memref<5xf32>
34+
%1 = memref.alloc() : memref<5xf32>
35+
%2 = memref.alloc() : memref<5xf32>
36+
%3 = memref.cast %0 : memref<5xf32> to memref<?xf32>
37+
%4 = memref.cast %1 : memref<5xf32> to memref<?xf32>
38+
%5 = memref.cast %2 : memref<5xf32> to memref<?xf32>
3939
scf.for %i = %c0 to %c5 step %c1 {
40-
store %cf1dot23, %3[%i] : memref<?xf32>
41-
store %cf1dot23, %4[%i] : memref<?xf32>
40+
memref.store %cf1dot23, %3[%i] : memref<?xf32>
41+
memref.store %cf1dot23, %4[%i] : memref<?xf32>
4242
}
43-
%6 = memref_cast %3 : memref<?xf32> to memref<*xf32>
44-
%7 = memref_cast %4 : memref<?xf32> to memref<*xf32>
45-
%8 = memref_cast %5 : memref<?xf32> to memref<*xf32>
43+
%6 = memref.cast %3 : memref<?xf32> to memref<*xf32>
44+
%7 = memref.cast %4 : memref<?xf32> to memref<*xf32>
45+
%8 = memref.cast %5 : memref<?xf32> to memref<*xf32>
4646
gpu.host_register %6 : memref<*xf32>
4747
gpu.host_register %7 : memref<*xf32>
4848
gpu.host_register %8 : memref<*xf32>

‎mlir/test/Integration/GPU/ROCM/vector-transferops.mlir

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -59,19 +59,19 @@ func @main() {
5959
%cf1 = arith.constant 1.0 : f32
6060
%cf1dot23 = arith.constant 1.23 : f32
6161

62-
%arg0 = alloc() : memref<4xf32>
63-
%arg1 = alloc() : memref<4xf32>
62+
%arg0 = memref.alloc() : memref<4xf32>
63+
%arg1 = memref.alloc() : memref<4xf32>
6464

65-
%22 = memref_cast %arg0 : memref<4xf32> to memref<?xf32>
66-
%23 = memref_cast %arg1 : memref<4xf32> to memref<?xf32>
65+
%22 = memref.cast %arg0 : memref<4xf32> to memref<?xf32>
66+
%23 = memref.cast %arg1 : memref<4xf32> to memref<?xf32>
6767

6868
scf.for %i = %c0 to %c4 step %c1 {
69-
store %cf1dot23, %22[%i] : memref<?xf32>
70-
store %cf1dot23, %23[%i] : memref<?xf32>
69+
memref.store %cf1dot23, %22[%i] : memref<?xf32>
70+
memref.store %cf1dot23, %23[%i] : memref<?xf32>
7171
}
7272

73-
%cast0 = memref_cast %22 : memref<?xf32> to memref<*xf32>
74-
%cast1 = memref_cast %23 : memref<?xf32> to memref<*xf32>
73+
%cast0 = memref.cast %22 : memref<?xf32> to memref<*xf32>
74+
%cast1 = memref.cast %23 : memref<?xf32> to memref<*xf32>
7575

7676
gpu.host_register %cast0 : memref<*xf32>
7777
gpu.host_register %cast1 : memref<*xf32>

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