@@ -69,7 +69,8 @@ def Log2 : SDNodeXForm<imm, [{
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//===----------------------------------------------------------------------===//
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class NDSRVInstBB<bit cs, string opcodestr>
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- : RVInst<(outs), (ins GPR:$rs1, uimmlog2xlen:$cimm, bare_simm11_lsb0:$imm10),
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+ : RVInst<(outs),
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+ (ins GPR:$rs1, uimmlog2xlen:$cimm, bare_simm11_lsb0:$imm10),
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opcodestr, "$rs1, $cimm, $imm10", [], InstFormatNDS_BRANCH_10>,
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Sched<[WriteJmp, ReadIALU]> {
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bits<10> imm10;
@@ -117,7 +118,8 @@ class NDSRVInstBC<bits<3> funct3, string opcodestr>
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}
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class NDSRVInstBFO<bits<3> funct3, string opcodestr>
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- : RVInst<(outs GPR:$rd), (ins GPR:$rs1, uimmlog2xlen:$msb, uimmlog2xlen:$lsb),
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+ : RVInst<(outs GPR:$rd),
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+ (ins GPR:$rs1, uimmlog2xlen:$msb, uimmlog2xlen:$lsb),
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opcodestr, "$rd, $rs1, $msb, $lsb", [], InstFormatOther>,
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Sched<[WriteIALU, ReadIALU]> {
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bits<5> rd;
@@ -409,7 +411,8 @@ multiclass VPseudoVNCVT_BF16_S {
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defvar constraint = "@earlyclobber $rd";
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foreach m = MxListFW in {
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let VLMul = m.value, SEW=16 in
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- def "_" # m.MX : VPseudoUnaryNoMaskRoundingMode<m.vrclass, m.wvrclass, constraint>,
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+ def "_" # m.MX : VPseudoUnaryNoMaskRoundingMode<m.vrclass, m.wvrclass,
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+ constraint>,
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SchedUnary<"WriteVFNCvtFToFV", "ReadVFNCvtFToFV", m.MX, 16,
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forcePassthruRead=true>;
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}
@@ -420,8 +423,10 @@ multiclass VPatConversionS_BF16<string intrinsic, string instruction> {
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defvar fvti = fvtiToFWti.Vti;
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defvar fwti = fvtiToFWti.Wti;
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let Predicates = [HasVendorXAndesVBFHCvt] in
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- def : VPatUnaryNoMask<intrinsic, instruction, "BF16", fwti.Vector, fvti.Vector,
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- fvti.Log2SEW, fvti.LMul, fwti.RegClass, fvti.RegClass>;
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+ def : VPatUnaryNoMask<intrinsic, instruction, "BF16",
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+ fwti.Vector, fvti.Vector,
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+ fvti.Log2SEW, fvti.LMul,
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+ fwti.RegClass, fvti.RegClass>;
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}
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}
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@@ -430,8 +435,10 @@ multiclass VPatConversionBF16_S<string intrinsic, string instruction> {
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defvar fvti = fvtiToFWti.Vti;
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defvar fwti = fvtiToFWti.Wti;
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let Predicates = [HasVendorXAndesVBFHCvt] in
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- def : VPatUnaryNoMaskRoundingMode<intrinsic, instruction, "S", fvti.Vector, fwti.Vector,
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- fvti.Log2SEW, fvti.LMul, fvti.RegClass, fwti.RegClass>;
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+ def : VPatUnaryNoMaskRoundingMode<intrinsic, instruction, "S",
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+ fvti.Vector, fwti.Vector,
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+ fvti.Log2SEW, fvti.LMul,
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+ fvti.RegClass, fwti.RegClass>;
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}
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}
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@@ -451,7 +458,8 @@ multiclass VPatVFPMADBinaryV_VX_RM<string intrinsic, string instruction,
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list<VTypeInfo> vtilist> {
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foreach vti = vtilist in {
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defvar kind = "V"#vti.ScalarSuffix;
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- defm : VPatBinaryRoundingMode<intrinsic, instruction#"_"#kind#"_"#vti.LMul.MX,
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+ defm : VPatBinaryRoundingMode<intrinsic,
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+ instruction#"_"#kind#"_"#vti.LMul.MX,
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vti.Vector, vti.Vector, f32, vti.Mask,
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vti.Log2SEW, vti.RegClass,
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vti.RegClass, FPR32>;
@@ -639,17 +647,21 @@ defm PseudoNDS_VFWCVT_S_BF16 : VPseudoVWCVT_S_BF16;
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defm PseudoNDS_VFNCVT_BF16_S : VPseudoVNCVT_BF16_S;
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} // Predicates = [HasVendorXAndesVBFHCvt]
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- defm : VPatConversionS_BF16<"int_riscv_nds_vfwcvt_s_bf16", "PseudoNDS_VFWCVT_S">;
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- defm : VPatConversionBF16_S<"int_riscv_nds_vfncvt_bf16_s", "PseudoNDS_VFNCVT_BF16">;
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+ defm : VPatConversionS_BF16<"int_riscv_nds_vfwcvt_s_bf16",
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+ "PseudoNDS_VFWCVT_S">;
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+ defm : VPatConversionBF16_S<"int_riscv_nds_vfncvt_bf16_s",
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+ "PseudoNDS_VFNCVT_BF16">;
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let Predicates = [HasVendorXAndesVPackFPH],
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mayRaiseFPException = true in {
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defm PseudoNDS_VFPMADT : VPseudoVFPMAD_VF_RM;
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defm PseudoNDS_VFPMADB : VPseudoVFPMAD_VF_RM;
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} // Predicates = [HasVendorXAndesVPackFPH]
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- defm : VPatVFPMADBinaryV_VX_RM<"int_riscv_nds_vfpmadt", "PseudoNDS_VFPMADT", AllFP16Vectors>;
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- defm : VPatVFPMADBinaryV_VX_RM<"int_riscv_nds_vfpmadb", "PseudoNDS_VFPMADB", AllFP16Vectors>;
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+ defm : VPatVFPMADBinaryV_VX_RM<"int_riscv_nds_vfpmadt", "PseudoNDS_VFPMADT",
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+ AllFP16Vectors>;
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+ defm : VPatVFPMADBinaryV_VX_RM<"int_riscv_nds_vfpmadb", "PseudoNDS_VFPMADB",
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+ AllFP16Vectors>;
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let Predicates = [HasVendorXAndesVDot] in {
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defm PseudoNDS_VD4DOTS : VPseudoVD4DOT_VV;
@@ -669,9 +681,12 @@ defset list<VTypeInfoToWide> AllQuadWidenableVD4DOTVectors = {
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def : VTypeInfoToWide<VI16M8, VI64M8>;
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}
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- defm : VPatTernaryVD4DOT_VV<"int_riscv_nds_vd4dots", "PseudoNDS_VD4DOTS", AllQuadWidenableVD4DOTVectors>;
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- defm : VPatTernaryVD4DOT_VV<"int_riscv_nds_vd4dotu", "PseudoNDS_VD4DOTU", AllQuadWidenableVD4DOTVectors>;
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- defm : VPatTernaryVD4DOT_VV<"int_riscv_nds_vd4dotsu", "PseudoNDS_VD4DOTSU", AllQuadWidenableVD4DOTVectors>;
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+ defm : VPatTernaryVD4DOT_VV<"int_riscv_nds_vd4dots", "PseudoNDS_VD4DOTS",
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+ AllQuadWidenableVD4DOTVectors>;
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+ defm : VPatTernaryVD4DOT_VV<"int_riscv_nds_vd4dotu", "PseudoNDS_VD4DOTU",
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+ AllQuadWidenableVD4DOTVectors>;
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+ defm : VPatTernaryVD4DOT_VV<"int_riscv_nds_vd4dotsu", "PseudoNDS_VD4DOTSU",
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+ AllQuadWidenableVD4DOTVectors>;
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//===----------------------------------------------------------------------===//
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// Pseudo-instructions for SFB (Short Forward Branch)
@@ -681,12 +696,14 @@ let Predicates = [HasShortForwardBranchOpt], hasSideEffects = 0,
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mayLoad = 0, mayStore = 0, Size = 8, Constraints = "$dst = $falsev" in {
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def PseudoCCNDS_BFOS : Pseudo<(outs GPR:$dst),
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(ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc,
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- GPR:$falsev, GPR:$rs1, uimmlog2xlen:$msb, uimmlog2xlen:$lsb), []>,
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+ GPR:$falsev, GPR:$rs1,
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+ uimmlog2xlen:$msb, uimmlog2xlen:$lsb), []>,
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Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU,
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ReadSFBALU]>;
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def PseudoCCNDS_BFOZ : Pseudo<(outs GPR:$dst),
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(ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc,
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- GPR:$falsev, GPR:$rs1, uimmlog2xlen:$msb, uimmlog2xlen:$lsb), []>,
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+ GPR:$falsev, GPR:$rs1,
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+ uimmlog2xlen:$msb, uimmlog2xlen:$lsb), []>,
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Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU,
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ReadSFBALU]>;
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}
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