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[RISCV] Trim line to 80 chars in RISCVInstrInfoXAndes.td. NFC.
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llvm/lib/Target/RISCV/RISCVInstrInfoXAndes.td

Lines changed: 34 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -69,7 +69,8 @@ def Log2 : SDNodeXForm<imm, [{
6969
//===----------------------------------------------------------------------===//
7070

7171
class NDSRVInstBB<bit cs, string opcodestr>
72-
: RVInst<(outs), (ins GPR:$rs1, uimmlog2xlen:$cimm, bare_simm11_lsb0:$imm10),
72+
: RVInst<(outs),
73+
(ins GPR:$rs1, uimmlog2xlen:$cimm, bare_simm11_lsb0:$imm10),
7374
opcodestr, "$rs1, $cimm, $imm10", [], InstFormatNDS_BRANCH_10>,
7475
Sched<[WriteJmp, ReadIALU]> {
7576
bits<10> imm10;
@@ -117,7 +118,8 @@ class NDSRVInstBC<bits<3> funct3, string opcodestr>
117118
}
118119

119120
class NDSRVInstBFO<bits<3> funct3, string opcodestr>
120-
: RVInst<(outs GPR:$rd), (ins GPR:$rs1, uimmlog2xlen:$msb, uimmlog2xlen:$lsb),
121+
: RVInst<(outs GPR:$rd),
122+
(ins GPR:$rs1, uimmlog2xlen:$msb, uimmlog2xlen:$lsb),
121123
opcodestr, "$rd, $rs1, $msb, $lsb", [], InstFormatOther>,
122124
Sched<[WriteIALU, ReadIALU]> {
123125
bits<5> rd;
@@ -409,7 +411,8 @@ multiclass VPseudoVNCVT_BF16_S {
409411
defvar constraint = "@earlyclobber $rd";
410412
foreach m = MxListFW in {
411413
let VLMul = m.value, SEW=16 in
412-
def "_" # m.MX : VPseudoUnaryNoMaskRoundingMode<m.vrclass, m.wvrclass, constraint>,
414+
def "_" # m.MX : VPseudoUnaryNoMaskRoundingMode<m.vrclass, m.wvrclass,
415+
constraint>,
413416
SchedUnary<"WriteVFNCvtFToFV", "ReadVFNCvtFToFV", m.MX, 16,
414417
forcePassthruRead=true>;
415418
}
@@ -420,8 +423,10 @@ multiclass VPatConversionS_BF16<string intrinsic, string instruction> {
420423
defvar fvti = fvtiToFWti.Vti;
421424
defvar fwti = fvtiToFWti.Wti;
422425
let Predicates = [HasVendorXAndesVBFHCvt] in
423-
def : VPatUnaryNoMask<intrinsic, instruction, "BF16", fwti.Vector, fvti.Vector,
424-
fvti.Log2SEW, fvti.LMul, fwti.RegClass, fvti.RegClass>;
426+
def : VPatUnaryNoMask<intrinsic, instruction, "BF16",
427+
fwti.Vector, fvti.Vector,
428+
fvti.Log2SEW, fvti.LMul,
429+
fwti.RegClass, fvti.RegClass>;
425430
}
426431
}
427432

@@ -430,8 +435,10 @@ multiclass VPatConversionBF16_S<string intrinsic, string instruction> {
430435
defvar fvti = fvtiToFWti.Vti;
431436
defvar fwti = fvtiToFWti.Wti;
432437
let Predicates = [HasVendorXAndesVBFHCvt] in
433-
def : VPatUnaryNoMaskRoundingMode<intrinsic, instruction, "S", fvti.Vector, fwti.Vector,
434-
fvti.Log2SEW, fvti.LMul, fvti.RegClass, fwti.RegClass>;
438+
def : VPatUnaryNoMaskRoundingMode<intrinsic, instruction, "S",
439+
fvti.Vector, fwti.Vector,
440+
fvti.Log2SEW, fvti.LMul,
441+
fvti.RegClass, fwti.RegClass>;
435442
}
436443
}
437444

@@ -451,7 +458,8 @@ multiclass VPatVFPMADBinaryV_VX_RM<string intrinsic, string instruction,
451458
list<VTypeInfo> vtilist> {
452459
foreach vti = vtilist in {
453460
defvar kind = "V"#vti.ScalarSuffix;
454-
defm : VPatBinaryRoundingMode<intrinsic, instruction#"_"#kind#"_"#vti.LMul.MX,
461+
defm : VPatBinaryRoundingMode<intrinsic,
462+
instruction#"_"#kind#"_"#vti.LMul.MX,
455463
vti.Vector, vti.Vector, f32, vti.Mask,
456464
vti.Log2SEW, vti.RegClass,
457465
vti.RegClass, FPR32>;
@@ -639,17 +647,21 @@ defm PseudoNDS_VFWCVT_S_BF16 : VPseudoVWCVT_S_BF16;
639647
defm PseudoNDS_VFNCVT_BF16_S : VPseudoVNCVT_BF16_S;
640648
} // Predicates = [HasVendorXAndesVBFHCvt]
641649

642-
defm : VPatConversionS_BF16<"int_riscv_nds_vfwcvt_s_bf16", "PseudoNDS_VFWCVT_S">;
643-
defm : VPatConversionBF16_S<"int_riscv_nds_vfncvt_bf16_s", "PseudoNDS_VFNCVT_BF16">;
650+
defm : VPatConversionS_BF16<"int_riscv_nds_vfwcvt_s_bf16",
651+
"PseudoNDS_VFWCVT_S">;
652+
defm : VPatConversionBF16_S<"int_riscv_nds_vfncvt_bf16_s",
653+
"PseudoNDS_VFNCVT_BF16">;
644654

645655
let Predicates = [HasVendorXAndesVPackFPH],
646656
mayRaiseFPException = true in {
647657
defm PseudoNDS_VFPMADT : VPseudoVFPMAD_VF_RM;
648658
defm PseudoNDS_VFPMADB : VPseudoVFPMAD_VF_RM;
649659
} // Predicates = [HasVendorXAndesVPackFPH]
650660

651-
defm : VPatVFPMADBinaryV_VX_RM<"int_riscv_nds_vfpmadt", "PseudoNDS_VFPMADT", AllFP16Vectors>;
652-
defm : VPatVFPMADBinaryV_VX_RM<"int_riscv_nds_vfpmadb", "PseudoNDS_VFPMADB", AllFP16Vectors>;
661+
defm : VPatVFPMADBinaryV_VX_RM<"int_riscv_nds_vfpmadt", "PseudoNDS_VFPMADT",
662+
AllFP16Vectors>;
663+
defm : VPatVFPMADBinaryV_VX_RM<"int_riscv_nds_vfpmadb", "PseudoNDS_VFPMADB",
664+
AllFP16Vectors>;
653665

654666
let Predicates = [HasVendorXAndesVDot] in {
655667
defm PseudoNDS_VD4DOTS : VPseudoVD4DOT_VV;
@@ -669,9 +681,12 @@ defset list<VTypeInfoToWide> AllQuadWidenableVD4DOTVectors = {
669681
def : VTypeInfoToWide<VI16M8, VI64M8>;
670682
}
671683

672-
defm : VPatTernaryVD4DOT_VV<"int_riscv_nds_vd4dots", "PseudoNDS_VD4DOTS", AllQuadWidenableVD4DOTVectors>;
673-
defm : VPatTernaryVD4DOT_VV<"int_riscv_nds_vd4dotu", "PseudoNDS_VD4DOTU", AllQuadWidenableVD4DOTVectors>;
674-
defm : VPatTernaryVD4DOT_VV<"int_riscv_nds_vd4dotsu", "PseudoNDS_VD4DOTSU", AllQuadWidenableVD4DOTVectors>;
684+
defm : VPatTernaryVD4DOT_VV<"int_riscv_nds_vd4dots", "PseudoNDS_VD4DOTS",
685+
AllQuadWidenableVD4DOTVectors>;
686+
defm : VPatTernaryVD4DOT_VV<"int_riscv_nds_vd4dotu", "PseudoNDS_VD4DOTU",
687+
AllQuadWidenableVD4DOTVectors>;
688+
defm : VPatTernaryVD4DOT_VV<"int_riscv_nds_vd4dotsu", "PseudoNDS_VD4DOTSU",
689+
AllQuadWidenableVD4DOTVectors>;
675690

676691
//===----------------------------------------------------------------------===//
677692
// Pseudo-instructions for SFB (Short Forward Branch)
@@ -681,12 +696,14 @@ let Predicates = [HasShortForwardBranchOpt], hasSideEffects = 0,
681696
mayLoad = 0, mayStore = 0, Size = 8, Constraints = "$dst = $falsev" in {
682697
def PseudoCCNDS_BFOS : Pseudo<(outs GPR:$dst),
683698
(ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc,
684-
GPR:$falsev, GPR:$rs1, uimmlog2xlen:$msb, uimmlog2xlen:$lsb), []>,
699+
GPR:$falsev, GPR:$rs1,
700+
uimmlog2xlen:$msb, uimmlog2xlen:$lsb), []>,
685701
Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU,
686702
ReadSFBALU]>;
687703
def PseudoCCNDS_BFOZ : Pseudo<(outs GPR:$dst),
688704
(ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc,
689-
GPR:$falsev, GPR:$rs1, uimmlog2xlen:$msb, uimmlog2xlen:$lsb), []>,
705+
GPR:$falsev, GPR:$rs1,
706+
uimmlog2xlen:$msb, uimmlog2xlen:$lsb), []>,
690707
Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU,
691708
ReadSFBALU]>;
692709
}

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