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[CodeGen] Use MCRegister instead of MCPhysReg in RegisterMaskPair. NFC (#123688)
Update some other places to avoid implicit conversions this introduces, but I probably missed some.
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10 files changed

+14
-14
lines changed

10 files changed

+14
-14
lines changed

llvm/include/llvm/CodeGen/MachineBasicBlock.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -129,7 +129,7 @@ class MachineBasicBlock
129129
/// clearly as they both have an integer type.
130130
struct RegisterMaskPair {
131131
public:
132-
MCPhysReg PhysReg;
132+
MCRegister PhysReg;
133133
LaneBitmask LaneMask;
134134

135135
RegisterMaskPair(MCPhysReg PhysReg, LaneBitmask LaneMask)

llvm/lib/CodeGen/BranchFolding.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -381,7 +381,7 @@ void BranchFolder::replaceTailWithBranchTo(MachineBasicBlock::iterator OldInst,
381381
// full registers:
382382
assert(P.LaneMask == LaneBitmask::getAll() &&
383383
"Can only handle full register.");
384-
MCPhysReg Reg = P.PhysReg;
384+
MCRegister Reg = P.PhysReg;
385385
if (!LiveRegs.available(*MRI, Reg))
386386
continue;
387387
DebugLoc DL;

llvm/lib/CodeGen/LivePhysRegs.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -154,7 +154,7 @@ bool LivePhysRegs::available(const MachineRegisterInfo &MRI,
154154
/// Add live-in registers of basic block \p MBB to \p LiveRegs.
155155
void LivePhysRegs::addBlockLiveIns(const MachineBasicBlock &MBB) {
156156
for (const auto &LI : MBB.liveins()) {
157-
MCPhysReg Reg = LI.PhysReg;
157+
MCRegister Reg = LI.PhysReg;
158158
LaneBitmask Mask = LI.LaneMask;
159159
MCSubRegIndexIterator S(Reg, TRI);
160160
assert(Mask.any() && "Invalid livein mask");

llvm/lib/CodeGen/LiveVariables.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -576,7 +576,7 @@ void LiveVariables::runOnBlock(MachineBasicBlock *MBB, unsigned NumRegs) {
576576
// Mark live-in registers as live-in.
577577
SmallVector<Register, 4> Defs;
578578
for (const auto &LI : MBB->liveins()) {
579-
assert(Register::isPhysicalRegister(LI.PhysReg) &&
579+
assert(LI.PhysReg.isPhysical() &&
580580
"Cannot have a live-in virtual register!");
581581
HandlePhysRegDef(LI.PhysReg, nullptr, Defs);
582582
}

llvm/lib/CodeGen/MachineVerifier.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -894,7 +894,7 @@ MachineVerifier::visitMachineBasicBlockBefore(const MachineBasicBlock *MBB) {
894894
regsLive.clear();
895895
if (MRI->tracksLiveness()) {
896896
for (const auto &LI : MBB->liveins()) {
897-
if (!Register::isPhysicalRegister(LI.PhysReg)) {
897+
if (!LI.PhysReg.isPhysical()) {
898898
report("MBB live-in list contains non-physical register", MBB);
899899
continue;
900900
}
@@ -3448,7 +3448,7 @@ void MachineVerifier::visitMachineFunctionAfter() {
34483448
if (MRI->tracksLiveness())
34493449
for (const auto &MBB : *MF)
34503450
for (MachineBasicBlock::RegisterMaskPair P : MBB.liveins()) {
3451-
MCPhysReg LiveInReg = P.PhysReg;
3451+
MCRegister LiveInReg = P.PhysReg;
34523452
bool hasAliases = MCRegAliasIterator(LiveInReg, TRI, false).isValid();
34533453
if (hasAliases || isAllocatable(LiveInReg) || isReserved(LiveInReg))
34543454
continue;

llvm/lib/CodeGen/RDFLiveness.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -895,7 +895,7 @@ void Liveness::computeLiveIns() {
895895
void Liveness::resetLiveIns() {
896896
for (auto &B : DFG.getMF()) {
897897
// Remove all live-ins.
898-
std::vector<unsigned> T;
898+
std::vector<MCRegister> T;
899899
for (const MachineBasicBlock::RegisterMaskPair &LI : B.liveins())
900900
T.push_back(LI.PhysReg);
901901
for (auto I : T)
@@ -917,7 +917,7 @@ void Liveness::resetKills(MachineBasicBlock *B) {
917917
for (auto I : B->liveins()) {
918918
MCSubRegIndexIterator S(I.PhysReg, &TRI);
919919
if (!S.isValid()) {
920-
LV.set(I.PhysReg);
920+
LV.set(I.PhysReg.id());
921921
continue;
922922
}
923923
do {

llvm/lib/CodeGen/RegAllocFast.cpp

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -276,7 +276,7 @@ class RegAllocFastImpl {
276276
// Assign index for each instruction to quickly determine dominance.
277277
InstrPosIndexes PosIndexes;
278278

279-
void setPhysRegState(MCPhysReg PhysReg, unsigned NewState);
279+
void setPhysRegState(MCRegister PhysReg, unsigned NewState);
280280
bool isPhysRegFree(MCPhysReg PhysReg) const;
281281

282282
/// Mark a physreg as used in this instruction.
@@ -449,7 +449,7 @@ bool RegAllocFastImpl::shouldAllocateRegister(const Register Reg) const {
449449
return ShouldAllocateRegisterImpl(*TRI, *MRI, Reg);
450450
}
451451

452-
void RegAllocFastImpl::setPhysRegState(MCPhysReg PhysReg, unsigned NewState) {
452+
void RegAllocFastImpl::setPhysRegState(MCRegister PhysReg, unsigned NewState) {
453453
for (MCRegUnit Unit : TRI->regunits(PhysReg))
454454
RegUnitStates[Unit] = NewState;
455455
}
@@ -671,7 +671,7 @@ void RegAllocFastImpl::reloadAtBegin(MachineBasicBlock &MBB) {
671671
return;
672672

673673
for (MachineBasicBlock::RegisterMaskPair P : MBB.liveins()) {
674-
MCPhysReg Reg = P.PhysReg;
674+
MCRegister Reg = P.PhysReg;
675675
// Set state to live-in. This possibly overrides mappings to virtual
676676
// registers but we don't care anymore at this point.
677677
setPhysRegState(Reg, regLiveIn);

llvm/lib/Target/AArch64/AArch64CollectLOH.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -251,7 +251,7 @@ static bool supportLoadFromLiteral(const MachineInstr &MI) {
251251
/// Number of GPR registers traked by mapRegToGPRIndex()
252252
static const unsigned N_GPR_REGS = 31;
253253
/// Map register number to index from 0-30.
254-
static int mapRegToGPRIndex(MCPhysReg Reg) {
254+
static int mapRegToGPRIndex(MCRegister Reg) {
255255
static_assert(AArch64::X28 - AArch64::X0 + 3 == N_GPR_REGS, "Number of GPRs");
256256
static_assert(AArch64::W30 - AArch64::W0 + 1 == N_GPR_REGS, "Number of GPRs");
257257
if (AArch64::X0 <= Reg && Reg <= AArch64::X28)

llvm/lib/Target/Mips/MipsDelaySlotFiller.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -402,7 +402,7 @@ void RegDefsUses::addLiveOut(const MachineBasicBlock &MBB,
402402
for (const MachineBasicBlock *S : MBB.successors())
403403
if (S != &SuccBB)
404404
for (const auto &LI : S->liveins())
405-
Uses.set(LI.PhysReg);
405+
Uses.set(LI.PhysReg.id());
406406
}
407407

408408
bool RegDefsUses::update(const MachineInstr &MI, unsigned Begin, unsigned End) {

llvm/lib/Target/X86/X86FrameLowering.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -174,7 +174,7 @@ static unsigned getPOP2Opcode(const X86Subtarget &ST) {
174174

175175
static bool isEAXLiveIn(MachineBasicBlock &MBB) {
176176
for (MachineBasicBlock::RegisterMaskPair RegMask : MBB.liveins()) {
177-
unsigned Reg = RegMask.PhysReg;
177+
MCRegister Reg = RegMask.PhysReg;
178178

179179
if (Reg == X86::RAX || Reg == X86::EAX || Reg == X86::AX ||
180180
Reg == X86::AH || Reg == X86::AL)

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