removed test cases with undef

Author: jyli0116

llvm/test/CodeGen/AArch64/GlobalISel/combine-sdiv.ll

@@ -874,84 +874,6 @@ define <4 x i32> @combine_vec_sdiv_by_pow2b_PosAndNeg(<4 x i32> %x) {
   ret <4 x i32> %1
 }
 
-define <4 x i32> @combine_vec_sdiv_by_pow2b_undef1(<4 x i32> %x) {
-; CHECK-SD-LABEL: combine_vec_sdiv_by_pow2b_undef1:
-; CHECK-SD:       // %bb.0:
-; CHECK-SD-NEXT:    ret
-;
-; CHECK-GI-LABEL: combine_vec_sdiv_by_pow2b_undef1:
-; CHECK-GI:       // %bb.0:
-; CHECK-GI-NEXT:    mov w10, v0.s[1]
-; CHECK-GI-NEXT:    fmov w9, s0
-; CHECK-GI-NEXT:    mov w8, #-4 // =0xfffffffc
-; CHECK-GI-NEXT:    mov w11, v0.s[3]
-; CHECK-GI-NEXT:    mov w12, #-16 // =0xfffffff0
-; CHECK-GI-NEXT:    sdiv w9, w9, w8
-; CHECK-GI-NEXT:    sdiv w8, w10, w8
-; CHECK-GI-NEXT:    mov w10, v0.s[2]
-; CHECK-GI-NEXT:    fmov s0, w9
-; CHECK-GI-NEXT:    sdiv w10, w10, w8
-; CHECK-GI-NEXT:    mov v0.s[1], w8
-; CHECK-GI-NEXT:    sdiv w8, w11, w12
-; CHECK-GI-NEXT:    mov v0.s[2], w10
-; CHECK-GI-NEXT:    mov v0.s[3], w8
-; CHECK-GI-NEXT:    ret
-  %1 = sdiv <4 x i32> %x, <i32 undef, i32 -4, i32 undef, i32 -16>
-  ret <4 x i32> %1
-}
-
-define <4 x i32> @combine_vec_sdiv_by_pow2b_undef2(<4 x i32> %x) {
-; CHECK-SD-LABEL: combine_vec_sdiv_by_pow2b_undef2:
-; CHECK-SD:       // %bb.0:
-; CHECK-SD-NEXT:    ret
-;
-; CHECK-GI-LABEL: combine_vec_sdiv_by_pow2b_undef2:
-; CHECK-GI:       // %bb.0:
-; CHECK-GI-NEXT:    mov w10, v0.s[1]
-; CHECK-GI-NEXT:    fmov w9, s0
-; CHECK-GI-NEXT:    mov w8, #4 // =0x4
-; CHECK-GI-NEXT:    mov w11, v0.s[3]
-; CHECK-GI-NEXT:    mov w12, #16 // =0x10
-; CHECK-GI-NEXT:    sdiv w9, w9, w8
-; CHECK-GI-NEXT:    sdiv w8, w10, w8
-; CHECK-GI-NEXT:    mov w10, v0.s[2]
-; CHECK-GI-NEXT:    fmov s0, w9
-; CHECK-GI-NEXT:    sdiv w10, w10, w8
-; CHECK-GI-NEXT:    mov v0.s[1], w8
-; CHECK-GI-NEXT:    sdiv w8, w11, w12
-; CHECK-GI-NEXT:    mov v0.s[2], w10
-; CHECK-GI-NEXT:    mov v0.s[3], w8
-; CHECK-GI-NEXT:    ret
-  %1 = sdiv <4 x i32> %x, <i32 undef, i32 4, i32 undef, i32 16>
-  ret <4 x i32> %1
-}
-
-define <4 x i32> @combine_vec_sdiv_by_pow2b_undef3(<4 x i32> %x) {
-; CHECK-SD-LABEL: combine_vec_sdiv_by_pow2b_undef3:
-; CHECK-SD:       // %bb.0:
-; CHECK-SD-NEXT:    ret
-;
-; CHECK-GI-LABEL: combine_vec_sdiv_by_pow2b_undef3:
-; CHECK-GI:       // %bb.0:
-; CHECK-GI-NEXT:    mov w10, v0.s[1]
-; CHECK-GI-NEXT:    fmov w9, s0
-; CHECK-GI-NEXT:    mov w8, #-4 // =0xfffffffc
-; CHECK-GI-NEXT:    mov w11, v0.s[3]
-; CHECK-GI-NEXT:    mov w12, #16 // =0x10
-; CHECK-GI-NEXT:    sdiv w9, w9, w8
-; CHECK-GI-NEXT:    sdiv w8, w10, w8
-; CHECK-GI-NEXT:    mov w10, v0.s[2]
-; CHECK-GI-NEXT:    fmov s0, w9
-; CHECK-GI-NEXT:    sdiv w10, w10, w8
-; CHECK-GI-NEXT:    mov v0.s[1], w8
-; CHECK-GI-NEXT:    sdiv w8, w11, w12
-; CHECK-GI-NEXT:    mov v0.s[2], w10
-; CHECK-GI-NEXT:    mov v0.s[3], w8
-; CHECK-GI-NEXT:    ret
-  %1 = sdiv <4 x i32> %x, <i32 undef, i32 -4, i32 undef, i32 16>
-  ret <4 x i32> %1
-}
-
 ; PR37119
 define <16 x i8> @non_splat_minus_one_divisor_0(<16 x i8> %A) {
 ; CHECK-SD-LABEL: non_splat_minus_one_divisor_0: