@@ -874,84 +874,6 @@ define <4 x i32> @combine_vec_sdiv_by_pow2b_PosAndNeg(<4 x i32> %x) {
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ret <4 x i32 > %1
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}
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- define <4 x i32 > @combine_vec_sdiv_by_pow2b_undef1 (<4 x i32 > %x ) {
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- ; CHECK-SD-LABEL: combine_vec_sdiv_by_pow2b_undef1:
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- ; CHECK-SD: // %bb.0:
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- ; CHECK-SD-NEXT: ret
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- ;
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- ; CHECK-GI-LABEL: combine_vec_sdiv_by_pow2b_undef1:
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- ; CHECK-GI: // %bb.0:
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- ; CHECK-GI-NEXT: mov w10, v0.s[1]
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- ; CHECK-GI-NEXT: fmov w9, s0
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- ; CHECK-GI-NEXT: mov w8, #-4 // =0xfffffffc
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- ; CHECK-GI-NEXT: mov w11, v0.s[3]
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- ; CHECK-GI-NEXT: mov w12, #-16 // =0xfffffff0
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- ; CHECK-GI-NEXT: sdiv w9, w9, w8
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- ; CHECK-GI-NEXT: sdiv w8, w10, w8
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- ; CHECK-GI-NEXT: mov w10, v0.s[2]
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- ; CHECK-GI-NEXT: fmov s0, w9
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- ; CHECK-GI-NEXT: sdiv w10, w10, w8
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- ; CHECK-GI-NEXT: mov v0.s[1], w8
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- ; CHECK-GI-NEXT: sdiv w8, w11, w12
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- ; CHECK-GI-NEXT: mov v0.s[2], w10
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- ; CHECK-GI-NEXT: mov v0.s[3], w8
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- ; CHECK-GI-NEXT: ret
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- %1 = sdiv <4 x i32 > %x , <i32 undef , i32 -4 , i32 undef , i32 -16 >
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- ret <4 x i32 > %1
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- }
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-
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- define <4 x i32 > @combine_vec_sdiv_by_pow2b_undef2 (<4 x i32 > %x ) {
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- ; CHECK-SD-LABEL: combine_vec_sdiv_by_pow2b_undef2:
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- ; CHECK-SD: // %bb.0:
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- ; CHECK-SD-NEXT: ret
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- ;
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- ; CHECK-GI-LABEL: combine_vec_sdiv_by_pow2b_undef2:
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- ; CHECK-GI: // %bb.0:
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- ; CHECK-GI-NEXT: mov w10, v0.s[1]
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- ; CHECK-GI-NEXT: fmov w9, s0
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- ; CHECK-GI-NEXT: mov w8, #4 // =0x4
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- ; CHECK-GI-NEXT: mov w11, v0.s[3]
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- ; CHECK-GI-NEXT: mov w12, #16 // =0x10
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- ; CHECK-GI-NEXT: sdiv w9, w9, w8
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- ; CHECK-GI-NEXT: sdiv w8, w10, w8
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- ; CHECK-GI-NEXT: mov w10, v0.s[2]
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- ; CHECK-GI-NEXT: fmov s0, w9
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- ; CHECK-GI-NEXT: sdiv w10, w10, w8
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- ; CHECK-GI-NEXT: mov v0.s[1], w8
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- ; CHECK-GI-NEXT: sdiv w8, w11, w12
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- ; CHECK-GI-NEXT: mov v0.s[2], w10
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- ; CHECK-GI-NEXT: mov v0.s[3], w8
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- ; CHECK-GI-NEXT: ret
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- %1 = sdiv <4 x i32 > %x , <i32 undef , i32 4 , i32 undef , i32 16 >
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- ret <4 x i32 > %1
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- }
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-
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- define <4 x i32 > @combine_vec_sdiv_by_pow2b_undef3 (<4 x i32 > %x ) {
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- ; CHECK-SD-LABEL: combine_vec_sdiv_by_pow2b_undef3:
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- ; CHECK-SD: // %bb.0:
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- ; CHECK-SD-NEXT: ret
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- ;
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- ; CHECK-GI-LABEL: combine_vec_sdiv_by_pow2b_undef3:
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- ; CHECK-GI: // %bb.0:
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- ; CHECK-GI-NEXT: mov w10, v0.s[1]
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- ; CHECK-GI-NEXT: fmov w9, s0
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- ; CHECK-GI-NEXT: mov w8, #-4 // =0xfffffffc
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- ; CHECK-GI-NEXT: mov w11, v0.s[3]
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- ; CHECK-GI-NEXT: mov w12, #16 // =0x10
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- ; CHECK-GI-NEXT: sdiv w9, w9, w8
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- ; CHECK-GI-NEXT: sdiv w8, w10, w8
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- ; CHECK-GI-NEXT: mov w10, v0.s[2]
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- ; CHECK-GI-NEXT: fmov s0, w9
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- ; CHECK-GI-NEXT: sdiv w10, w10, w8
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- ; CHECK-GI-NEXT: mov v0.s[1], w8
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- ; CHECK-GI-NEXT: sdiv w8, w11, w12
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- ; CHECK-GI-NEXT: mov v0.s[2], w10
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- ; CHECK-GI-NEXT: mov v0.s[3], w8
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- ; CHECK-GI-NEXT: ret
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- %1 = sdiv <4 x i32 > %x , <i32 undef , i32 -4 , i32 undef , i32 16 >
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- ret <4 x i32 > %1
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- }
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-
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; PR37119
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define <16 x i8 > @non_splat_minus_one_divisor_0 (<16 x i8 > %A ) {
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; CHECK-SD-LABEL: non_splat_minus_one_divisor_0:
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