[WASM] Remove redundant zero folding and fix test

- Remove redundant zero folding in performVSelectCombine()
- Fix fpclamptosat_vec.ll test with pre-legalization folding of Vselect.

Author: badumbatish

llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp

@@ -3213,26 +3213,18 @@ static SDValue performTruncateCombine(SDNode *N,
   return truncateVectorWithNARROW(OutVT, In, DL, DAG);
 }
 
-static SDValue performVSelectCombine(SDNode *N, SelectionDAG &DAG) {
+static SDValue performVSelectCombine(SDNode *N,
+                                     TargetLowering::DAGCombinerInfo &DCI) {
   // In the tablegen.td, vselect A B C -> bitselect B C A
 
-  // SCENARIO A
-  // vselect <0>, X, Y
-  // -> bitselect X, Y, <0>
-  // -> or (AND(X, <0>), AND(<Y>, !<0>))
-  // -> or (0, AND(<Y>, !<0>))
-  // -> AND(Y, !<0>)
-  // -> AND(Y, 1)
-  // -> Y
-
-  // SCENARIO B
+  // SCENARIO 1
   // vselect Y, <0>, X
   // -> bitselect <0>, X, Y
   // -> or (AND(<0>, Y), AND(<X>, !<Y>))
   // -> or (0, AND(<X>, !<Y>))
   // -> AND(<X>, !<Y>)
 
-  // SCENARIO C
+  // SCENARIO 2
   // vselect X, Y, <0>
   // -> bitselect Y, <0>, X
   // -> or (AND(Y, X), AND(<0>, !X))
@@ -3242,28 +3234,28 @@ static SDValue performVSelectCombine(SDNode *N, SelectionDAG &DAG) {
   using namespace llvm::SDPatternMatch;
   assert(N->getOpcode() == ISD::VSELECT);
 
+  // INFO: There is degradation in performance pre-legalization,
+  // fpclamptosat_vec.ll
+  if (DCI.isBeforeLegalize())
+    return SDValue();
+
   SDLoc DL(N);
 
   SDValue Cond = N->getOperand(0), LHS = N->getOperand(1),
           RHS = N->getOperand(2);
   EVT NVT = N->getValueType(0);
-
+  SelectionDAG &DAG = DCI.DAG;
   APInt SplatValue;
 
-  // SCENARIO A
-  if (ISD::isConstantSplatVector(Cond.getNode(), SplatValue) &&
-      SplatValue.isZero())
-    return RHS;
-
-  // SCENARIO B
+  // SCENARIO 1
   if (ISD::isConstantSplatVector(LHS.getNode(), SplatValue) &&
       SplatValue.isZero())
     return DAG.getNode(
         ISD::AND, DL, NVT,
         {RHS, DAG.getSExtOrTrunc(DAG.getNOT(DL, Cond, Cond.getValueType()), DL,
                                  NVT)});
 
-  // SCENARIO C
+  // SCENARIO 2
   if (ISD::isConstantSplatVector(RHS.getNode(), SplatValue) &&
       SplatValue.isZero())
     return DAG.getNode(ISD::AND, DL, NVT,
@@ -3567,7 +3559,7 @@ WebAssemblyTargetLowering::PerformDAGCombine(SDNode *N,
   default:
     return SDValue();
   case ISD::VSELECT:
-    return performVSelectCombine(N, DCI.DAG);
+    return performVSelectCombine(N, DCI);
   case ISD::BITCAST:
     return performBitcastCombine(N, DCI);
   case ISD::SETCC:

llvm/test/CodeGen/WebAssembly/fpclamptosat_vec.ll

@@ -106,12 +106,10 @@ define <2 x i32> @ustest_f64i32(<2 x double> %x) {
 ; CHECK-NEXT:    i64x2.lt_s
 ; CHECK-NEXT:    v128.bitselect
 ; CHECK-NEXT:    local.tee 0
-; CHECK-NEXT:    v128.const 0, 0
-; CHECK-NEXT:    local.tee 1
 ; CHECK-NEXT:    local.get 0
-; CHECK-NEXT:    local.get 1
+; CHECK-NEXT:    v128.const 0, 0
 ; CHECK-NEXT:    i64x2.gt_s
-; CHECK-NEXT:    v128.bitselect
+; CHECK-NEXT:    v128.and
 ; CHECK-NEXT:    local.get 0
 ; CHECK-NEXT:    i8x16.shuffle 0, 1, 2, 3, 8, 9, 10, 11, 0, 1, 2, 3, 0, 1, 2, 3
 ; CHECK-NEXT:    # fallthrough-return
@@ -1557,12 +1555,10 @@ define <2 x i32> @ustest_f64i32_mm(<2 x double> %x) {
 ; CHECK-NEXT:    i64x2.lt_s
 ; CHECK-NEXT:    v128.bitselect
 ; CHECK-NEXT:    local.tee 0
-; CHECK-NEXT:    v128.const 0, 0
-; CHECK-NEXT:    local.tee 1
 ; CHECK-NEXT:    local.get 0
-; CHECK-NEXT:    local.get 1
+; CHECK-NEXT:    v128.const 0, 0
 ; CHECK-NEXT:    i64x2.gt_s
-; CHECK-NEXT:    v128.bitselect
+; CHECK-NEXT:    v128.and
 ; CHECK-NEXT:    local.get 0
 ; CHECK-NEXT:    i8x16.shuffle 0, 1, 2, 3, 8, 9, 10, 11, 0, 1, 2, 3, 0, 1, 2, 3
 ; CHECK-NEXT:    # fallthrough-return