[RISCV] Fix schedule info for FMVP_D_X. (#140766)

fpetrogalli · web-flow · commit edd4317e9f48 · 2025-05-22T08:39:57.000-07:00
This binary instruction reads from two input registers.
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZfa.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZfa.td
@@ -144,7 +144,7 @@ let mayRaiseFPException = 0 in {
 def FMVH_X_D : FPUnaryOp_r<0b1110001, 0b00001, 0b000, GPR, FPR64, "fmvh.x.d">,
                Sched<[WriteFMovF64ToI64, ReadFMovF64ToI64]>;
 def FMVP_D_X : FPBinaryOp_rr<0b1011001, 0b000, FPR64, GPR, "fmvp.d.x">,
-               Sched<[WriteFMovI64ToF64, ReadFMovI64ToF64]>;
+               Sched<[WriteFMovI64ToF64, ReadFMovI64ToF64, ReadFMovI64ToF64]>;
 }
 
 let isCodeGenOnly = 1, mayRaiseFPException = 0 in

Original file line number	Diff line number	Diff line change
`@@ -144,7 +144,7 @@ let mayRaiseFPException = 0 in {`
`144`	`144`	`def FMVH_X_D : FPUnaryOp_r<0b1110001, 0b00001, 0b000, GPR, FPR64, "fmvh.x.d">,`
`145`	`145`	`Sched<[WriteFMovF64ToI64, ReadFMovF64ToI64]>;`
`146`	`146`	`def FMVP_D_X : FPBinaryOp_rr<0b1011001, 0b000, FPR64, GPR, "fmvp.d.x">,`
`147`		`- Sched<[WriteFMovI64ToF64, ReadFMovI64ToF64]>;`
	`147`	`+ Sched<[WriteFMovI64ToF64, ReadFMovI64ToF64, ReadFMovI64ToF64]>;`
`148`	`148`	`}`
`149`	`149`
`150`	`150`	`let isCodeGenOnly = 1, mayRaiseFPException = 0 in`