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[Clang][RISCV] Update all RVV intrinsic auto-generated test case with new script. NFC
This commit updates all intrinsics under `clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated` because the new script of `update_llc_test_checks.py` is generating many new lines differently. This NFC commit updates the test cases in a whole batch. Signed-off by: eop Chen <eop.chen@sifive.com>
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‎clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaaddu.c

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‎clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vadc.c

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‎clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vadd.c

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‎clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vand.c

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‎clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vasub.c

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‎clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vasubu.c

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‎clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcompress.c

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‎clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcpop.c

Lines changed: 43 additions & 29 deletions
Original file line numberDiff line numberDiff line change
@@ -1,4 +1,4 @@
1-
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
1+
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
22
// REQUIRES: riscv-registered-target
33
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \
44
// RUN: -target-feature +experimental-zvfh -disable-O0-optnone \
@@ -7,126 +7,140 @@
77

88
#include <riscv_vector.h>
99

10-
// CHECK-RV64-LABEL: @test_vcpop_m_b1(
10+
// CHECK-RV64-LABEL: define dso_local i64 @test_vcpop_m_b1
11+
// CHECK-RV64-SAME: (<vscale x 64 x i1> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
1112
// CHECK-RV64-NEXT: entry:
12-
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.vcpop.nxv64i1.i64(<vscale x 64 x i1> [[OP1:%.*]], i64 [[VL:%.*]])
13+
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.vcpop.nxv64i1.i64(<vscale x 64 x i1> [[OP1]], i64 [[VL]])
1314
// CHECK-RV64-NEXT: ret i64 [[TMP0]]
1415
//
1516
unsigned long test_vcpop_m_b1(vbool1_t op1, size_t vl) {
1617
return __riscv_vcpop_m_b1(op1, vl);
1718
}
1819

19-
// CHECK-RV64-LABEL: @test_vcpop_m_b2(
20+
// CHECK-RV64-LABEL: define dso_local i64 @test_vcpop_m_b2
21+
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2022
// CHECK-RV64-NEXT: entry:
21-
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.vcpop.nxv32i1.i64(<vscale x 32 x i1> [[OP1:%.*]], i64 [[VL:%.*]])
23+
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.vcpop.nxv32i1.i64(<vscale x 32 x i1> [[OP1]], i64 [[VL]])
2224
// CHECK-RV64-NEXT: ret i64 [[TMP0]]
2325
//
2426
unsigned long test_vcpop_m_b2(vbool2_t op1, size_t vl) {
2527
return __riscv_vcpop_m_b2(op1, vl);
2628
}
2729

28-
// CHECK-RV64-LABEL: @test_vcpop_m_b4(
30+
// CHECK-RV64-LABEL: define dso_local i64 @test_vcpop_m_b4
31+
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2932
// CHECK-RV64-NEXT: entry:
30-
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.vcpop.nxv16i1.i64(<vscale x 16 x i1> [[OP1:%.*]], i64 [[VL:%.*]])
33+
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.vcpop.nxv16i1.i64(<vscale x 16 x i1> [[OP1]], i64 [[VL]])
3134
// CHECK-RV64-NEXT: ret i64 [[TMP0]]
3235
//
3336
unsigned long test_vcpop_m_b4(vbool4_t op1, size_t vl) {
3437
return __riscv_vcpop_m_b4(op1, vl);
3538
}
3639

37-
// CHECK-RV64-LABEL: @test_vcpop_m_b8(
40+
// CHECK-RV64-LABEL: define dso_local i64 @test_vcpop_m_b8
41+
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
3842
// CHECK-RV64-NEXT: entry:
39-
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.vcpop.nxv8i1.i64(<vscale x 8 x i1> [[OP1:%.*]], i64 [[VL:%.*]])
43+
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.vcpop.nxv8i1.i64(<vscale x 8 x i1> [[OP1]], i64 [[VL]])
4044
// CHECK-RV64-NEXT: ret i64 [[TMP0]]
4145
//
4246
unsigned long test_vcpop_m_b8(vbool8_t op1, size_t vl) {
4347
return __riscv_vcpop_m_b8(op1, vl);
4448
}
4549

46-
// CHECK-RV64-LABEL: @test_vcpop_m_b16(
50+
// CHECK-RV64-LABEL: define dso_local i64 @test_vcpop_m_b16
51+
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
4752
// CHECK-RV64-NEXT: entry:
48-
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.vcpop.nxv4i1.i64(<vscale x 4 x i1> [[OP1:%.*]], i64 [[VL:%.*]])
53+
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.vcpop.nxv4i1.i64(<vscale x 4 x i1> [[OP1]], i64 [[VL]])
4954
// CHECK-RV64-NEXT: ret i64 [[TMP0]]
5055
//
5156
unsigned long test_vcpop_m_b16(vbool16_t op1, size_t vl) {
5257
return __riscv_vcpop_m_b16(op1, vl);
5358
}
5459

55-
// CHECK-RV64-LABEL: @test_vcpop_m_b32(
60+
// CHECK-RV64-LABEL: define dso_local i64 @test_vcpop_m_b32
61+
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
5662
// CHECK-RV64-NEXT: entry:
57-
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.vcpop.nxv2i1.i64(<vscale x 2 x i1> [[OP1:%.*]], i64 [[VL:%.*]])
63+
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.vcpop.nxv2i1.i64(<vscale x 2 x i1> [[OP1]], i64 [[VL]])
5864
// CHECK-RV64-NEXT: ret i64 [[TMP0]]
5965
//
6066
unsigned long test_vcpop_m_b32(vbool32_t op1, size_t vl) {
6167
return __riscv_vcpop_m_b32(op1, vl);
6268
}
6369

64-
// CHECK-RV64-LABEL: @test_vcpop_m_b64(
70+
// CHECK-RV64-LABEL: define dso_local i64 @test_vcpop_m_b64
71+
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
6572
// CHECK-RV64-NEXT: entry:
66-
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.vcpop.nxv1i1.i64(<vscale x 1 x i1> [[OP1:%.*]], i64 [[VL:%.*]])
73+
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.vcpop.nxv1i1.i64(<vscale x 1 x i1> [[OP1]], i64 [[VL]])
6774
// CHECK-RV64-NEXT: ret i64 [[TMP0]]
6875
//
6976
unsigned long test_vcpop_m_b64(vbool64_t op1, size_t vl) {
7077
return __riscv_vcpop_m_b64(op1, vl);
7178
}
7279

73-
// CHECK-RV64-LABEL: @test_vcpop_m_b1_m(
80+
// CHECK-RV64-LABEL: define dso_local i64 @test_vcpop_m_b1_m
81+
// CHECK-RV64-SAME: (<vscale x 64 x i1> [[MASK:%.*]], <vscale x 64 x i1> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
7482
// CHECK-RV64-NEXT: entry:
75-
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.vcpop.mask.nxv64i1.i64(<vscale x 64 x i1> [[OP1:%.*]], <vscale x 64 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
83+
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.vcpop.mask.nxv64i1.i64(<vscale x 64 x i1> [[OP1]], <vscale x 64 x i1> [[MASK]], i64 [[VL]])
7684
// CHECK-RV64-NEXT: ret i64 [[TMP0]]
7785
//
7886
unsigned long test_vcpop_m_b1_m(vbool1_t mask, vbool1_t op1, size_t vl) {
7987
return __riscv_vcpop_m_b1_m(mask, op1, vl);
8088
}
8189

82-
// CHECK-RV64-LABEL: @test_vcpop_m_b2_m(
90+
// CHECK-RV64-LABEL: define dso_local i64 @test_vcpop_m_b2_m
91+
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x i1> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
8392
// CHECK-RV64-NEXT: entry:
84-
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.vcpop.mask.nxv32i1.i64(<vscale x 32 x i1> [[OP1:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
93+
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.vcpop.mask.nxv32i1.i64(<vscale x 32 x i1> [[OP1]], <vscale x 32 x i1> [[MASK]], i64 [[VL]])
8594
// CHECK-RV64-NEXT: ret i64 [[TMP0]]
8695
//
8796
unsigned long test_vcpop_m_b2_m(vbool2_t mask, vbool2_t op1, size_t vl) {
8897
return __riscv_vcpop_m_b2_m(mask, op1, vl);
8998
}
9099

91-
// CHECK-RV64-LABEL: @test_vcpop_m_b4_m(
100+
// CHECK-RV64-LABEL: define dso_local i64 @test_vcpop_m_b4_m
101+
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i1> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
92102
// CHECK-RV64-NEXT: entry:
93-
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.vcpop.mask.nxv16i1.i64(<vscale x 16 x i1> [[OP1:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
103+
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.vcpop.mask.nxv16i1.i64(<vscale x 16 x i1> [[OP1]], <vscale x 16 x i1> [[MASK]], i64 [[VL]])
94104
// CHECK-RV64-NEXT: ret i64 [[TMP0]]
95105
//
96106
unsigned long test_vcpop_m_b4_m(vbool4_t mask, vbool4_t op1, size_t vl) {
97107
return __riscv_vcpop_m_b4_m(mask, op1, vl);
98108
}
99109

100-
// CHECK-RV64-LABEL: @test_vcpop_m_b8_m(
110+
// CHECK-RV64-LABEL: define dso_local i64 @test_vcpop_m_b8_m
111+
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i1> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
101112
// CHECK-RV64-NEXT: entry:
102-
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.vcpop.mask.nxv8i1.i64(<vscale x 8 x i1> [[OP1:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
113+
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.vcpop.mask.nxv8i1.i64(<vscale x 8 x i1> [[OP1]], <vscale x 8 x i1> [[MASK]], i64 [[VL]])
103114
// CHECK-RV64-NEXT: ret i64 [[TMP0]]
104115
//
105116
unsigned long test_vcpop_m_b8_m(vbool8_t mask, vbool8_t op1, size_t vl) {
106117
return __riscv_vcpop_m_b8_m(mask, op1, vl);
107118
}
108119

109-
// CHECK-RV64-LABEL: @test_vcpop_m_b16_m(
120+
// CHECK-RV64-LABEL: define dso_local i64 @test_vcpop_m_b16_m
121+
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i1> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
110122
// CHECK-RV64-NEXT: entry:
111-
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.vcpop.mask.nxv4i1.i64(<vscale x 4 x i1> [[OP1:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
123+
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.vcpop.mask.nxv4i1.i64(<vscale x 4 x i1> [[OP1]], <vscale x 4 x i1> [[MASK]], i64 [[VL]])
112124
// CHECK-RV64-NEXT: ret i64 [[TMP0]]
113125
//
114126
unsigned long test_vcpop_m_b16_m(vbool16_t mask, vbool16_t op1, size_t vl) {
115127
return __riscv_vcpop_m_b16_m(mask, op1, vl);
116128
}
117129

118-
// CHECK-RV64-LABEL: @test_vcpop_m_b32_m(
130+
// CHECK-RV64-LABEL: define dso_local i64 @test_vcpop_m_b32_m
131+
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i1> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
119132
// CHECK-RV64-NEXT: entry:
120-
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.vcpop.mask.nxv2i1.i64(<vscale x 2 x i1> [[OP1:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
133+
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.vcpop.mask.nxv2i1.i64(<vscale x 2 x i1> [[OP1]], <vscale x 2 x i1> [[MASK]], i64 [[VL]])
121134
// CHECK-RV64-NEXT: ret i64 [[TMP0]]
122135
//
123136
unsigned long test_vcpop_m_b32_m(vbool32_t mask, vbool32_t op1, size_t vl) {
124137
return __riscv_vcpop_m_b32_m(mask, op1, vl);
125138
}
126139

127-
// CHECK-RV64-LABEL: @test_vcpop_m_b64_m(
140+
// CHECK-RV64-LABEL: define dso_local i64 @test_vcpop_m_b64_m
141+
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i1> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
128142
// CHECK-RV64-NEXT: entry:
129-
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.vcpop.mask.nxv1i1.i64(<vscale x 1 x i1> [[OP1:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
143+
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.vcpop.mask.nxv1i1.i64(<vscale x 1 x i1> [[OP1]], <vscale x 1 x i1> [[MASK]], i64 [[VL]])
130144
// CHECK-RV64-NEXT: ret i64 [[TMP0]]
131145
//
132146
unsigned long test_vcpop_m_b64_m(vbool64_t mask, vbool64_t op1, size_t vl) {

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