@@ -2417,10 +2417,8 @@ unsigned RISCVTargetLowering::getVectorTypeBreakdownForCallingConv(
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// in the RISC-V ISA. May adjust compares to favor compare with 0 over compare
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// with 1/-1.
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static void translateSetCCForBranch(const SDLoc &DL, SDValue &LHS, SDValue &RHS,
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- ISD::CondCode &CC, SelectionDAG &DAG) {
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- const RISCVSubtarget &Subtarget =
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- DAG.getMachineFunction().getSubtarget<RISCVSubtarget>();
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-
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+ ISD::CondCode &CC, SelectionDAG &DAG,
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+ const RISCVSubtarget &Subtarget) {
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// If this is a single bit test that can't be handled by ANDI, shift the
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// bit to be tested to the MSB and perform a signed compare with 0.
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if (isIntEqualitySetCC(CC) && isNullConstant(RHS) &&
@@ -9238,7 +9236,7 @@ SDValue RISCVTargetLowering::lowerSELECT(SDValue Op, SelectionDAG &DAG) const {
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return DAG.getNode(ISD::SUB, DL, VT, FalseV, CondV);
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}
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- translateSetCCForBranch(DL, LHS, RHS, CCVal, DAG);
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+ translateSetCCForBranch(DL, LHS, RHS, CCVal, DAG, Subtarget );
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// 1 < x ? x : 1 -> 0 < x ? x : 1
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if (isOneConstant(LHS) && (CCVal == ISD::SETLT || CCVal == ISD::SETULT) &&
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RHS == TrueV && LHS == FalseV) {
@@ -9280,7 +9278,7 @@ SDValue RISCVTargetLowering::lowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
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SDValue RHS = CondV.getOperand(1);
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ISD::CondCode CCVal = cast<CondCodeSDNode>(CondV.getOperand(2))->get();
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- translateSetCCForBranch(DL, LHS, RHS, CCVal, DAG);
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+ translateSetCCForBranch(DL, LHS, RHS, CCVal, DAG, Subtarget );
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SDValue TargetCC = DAG.getCondCode(CCVal);
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return DAG.getNode(RISCVISD::BR_CC, DL, Op.getValueType(), Op.getOperand(0),
@@ -18224,7 +18222,7 @@ static bool combine_CC(SDValue &LHS, SDValue &RHS, SDValue &CC, const SDLoc &DL,
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RHS = LHS.getOperand(1);
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LHS = LHS.getOperand(0);
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- translateSetCCForBranch(DL, LHS, RHS, CCVal, DAG);
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+ translateSetCCForBranch(DL, LHS, RHS, CCVal, DAG, Subtarget );
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CC = DAG.getCondCode(CCVal);
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return true;
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