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[RISCV] Add isel patterns to use Zilsd for f64 load/store for Zdinx on RV32. (#139935)
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4 files changed

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-10
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‎llvm/lib/Target/RISCV/RISCVFeatures.td

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -187,6 +187,7 @@ def FeatureStdExtZilsd
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def HasStdExtZilsd : Predicate<"Subtarget->hasStdExtZilsd()">,
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AssemblerPredicate<(all_of FeatureStdExtZilsd),
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"'Zilsd' (Load/Store pair instructions)">;
190+
def NoHasStdExtZilsd : Predicate<"!Subtarget->hasStdExtZilsd()">;
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191192
// Multiply Extensions
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‎llvm/lib/Target/RISCV/RISCVInstrInfo.td

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -2210,6 +2210,13 @@ include "RISCVInstrInfoA.td"
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include "RISCVInstrInfoZa.td"
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include "RISCVInstrInfoZalasr.td"
22122212

2213+
// Integer
2214+
include "RISCVInstrInfoZimop.td"
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include "RISCVInstrInfoZicbo.td"
2216+
include "RISCVInstrInfoZicond.td"
2217+
include "RISCVInstrInfoZicfiss.td"
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include "RISCVInstrInfoZilsd.td"
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// Scalar FP
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include "RISCVInstrInfoF.td"
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include "RISCVInstrInfoD.td"
@@ -2226,13 +2233,6 @@ include "RISCVInstrInfoV.td"
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include "RISCVInstrInfoZvk.td"
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include "RISCVInstrInfoZvqdotq.td"
22282235

2229-
// Integer
2230-
include "RISCVInstrInfoZimop.td"
2231-
include "RISCVInstrInfoZicbo.td"
2232-
include "RISCVInstrInfoZicond.td"
2233-
include "RISCVInstrInfoZicfiss.td"
2234-
include "RISCVInstrInfoZilsd.td"
2235-
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// Compressed
22372237
include "RISCVInstrInfoC.td"
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include "RISCVInstrInfoZc.td"

‎llvm/lib/Target/RISCV/RISCVInstrInfoD.td

Lines changed: 11 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -531,15 +531,23 @@ def PseudoFROUND_D_IN32X : PseudoFROUND<FPR64IN32X, f64>;
531531
/// Loads
532532
let isCall = 0, mayLoad = 1, mayStore = 0, Size = 8, isCodeGenOnly = 1 in
533533
def PseudoRV32ZdinxLD : Pseudo<(outs GPRPair:$dst), (ins GPR:$rs1, simm12:$imm12), []>;
534-
def : Pat<(f64 (load (AddrRegImmINX (XLenVT GPR:$rs1), simm12:$imm12))),
535-
(PseudoRV32ZdinxLD GPR:$rs1, simm12:$imm12)>;
536534

537535
/// Stores
538536
let isCall = 0, mayLoad = 0, mayStore = 1, Size = 8, isCodeGenOnly = 1 in
539537
def PseudoRV32ZdinxSD : Pseudo<(outs), (ins GPRPair:$rs2, GPRNoX0:$rs1, simm12:$imm12), []>;
538+
} // Predicates = [HasStdExtZdinx, IsRV32]
539+
540+
let Predicates = [HasStdExtZdinx, NoHasStdExtZilsd, IsRV32] in {
541+
def : Pat<(f64 (load (AddrRegImmINX (XLenVT GPR:$rs1), simm12:$imm12))),
542+
(PseudoRV32ZdinxLD GPR:$rs1, simm12:$imm12)>;
540543
def : Pat<(store (f64 GPRPair:$rs2), (AddrRegImmINX (XLenVT GPR:$rs1), simm12:$imm12)),
541544
(PseudoRV32ZdinxSD GPRPair:$rs2, GPR:$rs1, simm12:$imm12)>;
542-
} // Predicates = [HasStdExtZdinx, IsRV32]
545+
}
546+
547+
let Predicates = [HasStdExtZdinx, HasStdExtZilsd, IsRV32] in {
548+
def : LdPat<load, LD_RV32, f64>;
549+
def : StPat<store, SD_RV32, GPRPair, f64>;
550+
}
543551

544552
let Predicates = [HasStdExtD, IsRV32] in {
545553

‎llvm/test/CodeGen/RISCV/double-mem.ll

Lines changed: 77 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -7,6 +7,8 @@
77
; RUN: -target-abi=ilp32 | FileCheck -check-prefixes=RV32IZFINXZDINX %s
88
; RUN: llc -mtriple=riscv64 -mattr=+zdinx -verify-machineinstrs < %s \
99
; RUN: -target-abi=lp64 | FileCheck -check-prefixes=RV64IZFINXZDINX %s
10+
; RUN: llc -mtriple=riscv32 -mattr=+zdinx,+zilsd -verify-machineinstrs < %s \
11+
; RUN: -target-abi=ilp32 | FileCheck -check-prefixes=RV32IZFINXZDINXZILSD %s
1012

1113
define dso_local double @fld(ptr %a) nounwind {
1214
; CHECKIFD-LABEL: fld:
@@ -31,6 +33,13 @@ define dso_local double @fld(ptr %a) nounwind {
3133
; RV64IZFINXZDINX-NEXT: ld a0, 24(a0)
3234
; RV64IZFINXZDINX-NEXT: fadd.d a0, a1, a0
3335
; RV64IZFINXZDINX-NEXT: ret
36+
;
37+
; RV32IZFINXZDINXZILSD-LABEL: fld:
38+
; RV32IZFINXZDINXZILSD: # %bb.0:
39+
; RV32IZFINXZDINXZILSD-NEXT: ld a2, 0(a0)
40+
; RV32IZFINXZDINXZILSD-NEXT: ld a0, 24(a0)
41+
; RV32IZFINXZDINXZILSD-NEXT: fadd.d a0, a2, a0
42+
; RV32IZFINXZDINXZILSD-NEXT: ret
3443
%1 = load double, ptr %a
3544
%2 = getelementptr double, ptr %a, i32 3
3645
%3 = load double, ptr %2
@@ -67,6 +76,17 @@ define dso_local void @fsd(ptr %a, double %b, double %c) nounwind {
6776
; RV64IZFINXZDINX-NEXT: sd a1, 0(a0)
6877
; RV64IZFINXZDINX-NEXT: sd a1, 64(a0)
6978
; RV64IZFINXZDINX-NEXT: ret
79+
;
80+
; RV32IZFINXZDINXZILSD-LABEL: fsd:
81+
; RV32IZFINXZDINXZILSD: # %bb.0:
82+
; RV32IZFINXZDINXZILSD-NEXT: mv a5, a4
83+
; RV32IZFINXZDINXZILSD-NEXT: mv a7, a2
84+
; RV32IZFINXZDINXZILSD-NEXT: mv a4, a3
85+
; RV32IZFINXZDINXZILSD-NEXT: mv a6, a1
86+
; RV32IZFINXZDINXZILSD-NEXT: fadd.d a2, a6, a4
87+
; RV32IZFINXZDINXZILSD-NEXT: sd a2, 0(a0)
88+
; RV32IZFINXZDINXZILSD-NEXT: sd a2, 64(a0)
89+
; RV32IZFINXZDINXZILSD-NEXT: ret
7090
; Use %b and %c in an FP op to ensure floating point registers are used, even
7191
; for the soft float ABI
7292
%1 = fadd double %b, %c
@@ -116,6 +136,17 @@ define dso_local double @fld_fsd_global(double %a, double %b) nounwind {
116136
; RV64IZFINXZDINX-NEXT: ld zero, 72(a2)
117137
; RV64IZFINXZDINX-NEXT: sd a0, 72(a2)
118138
; RV64IZFINXZDINX-NEXT: ret
139+
;
140+
; RV32IZFINXZDINXZILSD-LABEL: fld_fsd_global:
141+
; RV32IZFINXZDINXZILSD: # %bb.0:
142+
; RV32IZFINXZDINXZILSD-NEXT: lui a4, %hi(G)
143+
; RV32IZFINXZDINXZILSD-NEXT: fadd.d a0, a0, a2
144+
; RV32IZFINXZDINXZILSD-NEXT: ld a2, %lo(G)(a4)
145+
; RV32IZFINXZDINXZILSD-NEXT: addi a2, a4, %lo(G)
146+
; RV32IZFINXZDINXZILSD-NEXT: sd a0, %lo(G)(a4)
147+
; RV32IZFINXZDINXZILSD-NEXT: ld a4, 72(a2)
148+
; RV32IZFINXZDINXZILSD-NEXT: sd a0, 72(a2)
149+
; RV32IZFINXZDINXZILSD-NEXT: ret
119150
; Use %a and %b in an FP op to ensure floating point registers are used, even
120151
; for the soft float ABI
121152
%1 = fadd double %a, %b
@@ -164,6 +195,14 @@ define dso_local double @fld_fsd_constant(double %a) nounwind {
164195
; RV64IZFINXZDINX-NEXT: fadd.d a0, a0, a2
165196
; RV64IZFINXZDINX-NEXT: sd a0, -273(a1)
166197
; RV64IZFINXZDINX-NEXT: ret
198+
;
199+
; RV32IZFINXZDINXZILSD-LABEL: fld_fsd_constant:
200+
; RV32IZFINXZDINXZILSD: # %bb.0:
201+
; RV32IZFINXZDINXZILSD-NEXT: lui a2, 912092
202+
; RV32IZFINXZDINXZILSD-NEXT: ld a4, -273(a2)
203+
; RV32IZFINXZDINXZILSD-NEXT: fadd.d a0, a0, a4
204+
; RV32IZFINXZDINXZILSD-NEXT: sd a0, -273(a2)
205+
; RV32IZFINXZDINXZILSD-NEXT: ret
167206
%1 = inttoptr i32 3735928559 to ptr
168207
%2 = load volatile double, ptr %1
169208
%3 = fadd double %a, %2
@@ -237,6 +276,24 @@ define dso_local double @fld_stack(double %a) nounwind {
237276
; RV64IZFINXZDINX-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
238277
; RV64IZFINXZDINX-NEXT: addi sp, sp, 32
239278
; RV64IZFINXZDINX-NEXT: ret
279+
;
280+
; RV32IZFINXZDINXZILSD-LABEL: fld_stack:
281+
; RV32IZFINXZDINXZILSD: # %bb.0:
282+
; RV32IZFINXZDINXZILSD-NEXT: addi sp, sp, -32
283+
; RV32IZFINXZDINXZILSD-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
284+
; RV32IZFINXZDINXZILSD-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
285+
; RV32IZFINXZDINXZILSD-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
286+
; RV32IZFINXZDINXZILSD-NEXT: mv s1, a1
287+
; RV32IZFINXZDINXZILSD-NEXT: mv s0, a0
288+
; RV32IZFINXZDINXZILSD-NEXT: addi a0, sp, 8
289+
; RV32IZFINXZDINXZILSD-NEXT: call notdead
290+
; RV32IZFINXZDINXZILSD-NEXT: ld a0, 8(sp)
291+
; RV32IZFINXZDINXZILSD-NEXT: fadd.d a0, a0, s0
292+
; RV32IZFINXZDINXZILSD-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
293+
; RV32IZFINXZDINXZILSD-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
294+
; RV32IZFINXZDINXZILSD-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
295+
; RV32IZFINXZDINXZILSD-NEXT: addi sp, sp, 32
296+
; RV32IZFINXZDINXZILSD-NEXT: ret
240297
%1 = alloca double, align 8
241298
call void @notdead(ptr %1)
242299
%2 = load double, ptr %1
@@ -293,6 +350,18 @@ define dso_local void @fsd_stack(double %a, double %b) nounwind {
293350
; RV64IZFINXZDINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
294351
; RV64IZFINXZDINX-NEXT: addi sp, sp, 16
295352
; RV64IZFINXZDINX-NEXT: ret
353+
;
354+
; RV32IZFINXZDINXZILSD-LABEL: fsd_stack:
355+
; RV32IZFINXZDINXZILSD: # %bb.0:
356+
; RV32IZFINXZDINXZILSD-NEXT: addi sp, sp, -16
357+
; RV32IZFINXZDINXZILSD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
358+
; RV32IZFINXZDINXZILSD-NEXT: fadd.d a0, a0, a2
359+
; RV32IZFINXZDINXZILSD-NEXT: sd a0, 0(sp)
360+
; RV32IZFINXZDINXZILSD-NEXT: mv a0, sp
361+
; RV32IZFINXZDINXZILSD-NEXT: call notdead
362+
; RV32IZFINXZDINXZILSD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
363+
; RV32IZFINXZDINXZILSD-NEXT: addi sp, sp, 16
364+
; RV32IZFINXZDINXZILSD-NEXT: ret
296365
%1 = fadd double %a, %b ; force store from FPR64
297366
%2 = alloca double, align 8
298367
store double %1, ptr %2
@@ -321,6 +390,14 @@ define dso_local void @fsd_trunc(ptr %a, double %b) nounwind noinline optnone {
321390
; RV64IZFINXZDINX-NEXT: fcvt.s.d a1, a1
322391
; RV64IZFINXZDINX-NEXT: sw a1, 0(a0)
323392
; RV64IZFINXZDINX-NEXT: ret
393+
;
394+
; RV32IZFINXZDINXZILSD-LABEL: fsd_trunc:
395+
; RV32IZFINXZDINXZILSD: # %bb.0:
396+
; RV32IZFINXZDINXZILSD-NEXT: mv a3, a2
397+
; RV32IZFINXZDINXZILSD-NEXT: mv a2, a1
398+
; RV32IZFINXZDINXZILSD-NEXT: fcvt.s.d a1, a2
399+
; RV32IZFINXZDINXZILSD-NEXT: sw a1, 0(a0)
400+
; RV32IZFINXZDINXZILSD-NEXT: ret
324401
%1 = fptrunc double %b to float
325402
store float %1, ptr %a, align 4
326403
ret void

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