@@ -2133,12 +2133,10 @@ SDValue NVPTXTargetLowering::LowerBITCAST(SDValue Op, SelectionDAG &DAG) const {
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}
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if (FromVT == MVT::v2f32) {
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- assert (ToVT == MVT::i64 );
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-
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// A bitcast to i64 from v2f32.
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// See if we can legalize the operand.
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const SDValue &Operand = Op->getOperand (0 );
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- if (Operand.getOpcode () == ISD::BUILD_VECTOR) {
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+ if (ToVT == MVT:: i64 && Operand.getOpcode () == ISD::BUILD_VECTOR) {
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const SDValue &BVOp0 = Operand.getOperand (0 );
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const SDValue &BVOp1 = Operand.getOperand (1 );
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@@ -2267,11 +2265,11 @@ SDValue NVPTXTargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
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return DAG.getSelectCC (DL, Index, DAG.getIntPtrConstant (0 , DL), E0 , E1 ,
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ISD::CondCode::SETEQ);
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};
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- if (Vector.getOpcode () == ISD::BITCAST) {
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+ if (SDValue Pair = Vector.getOperand (0 );
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+ Vector.getOpcode () == ISD::BITCAST &&
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+ Pair.getOpcode () == ISD::BUILD_PAIR) {
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// peek through v2f32 = bitcast (i64 = build_pair (i32 A, i32 B))
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// where A:i32, B:i32 = CopyFromReg (i64 = F32X2 Operation ...)
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- SDValue Pair = Vector.getOperand (0 );
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- assert (Pair.getOpcode () == ISD::BUILD_PAIR);
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return DAG.getNode (ISD::BITCAST, DL, Op.getValueType (),
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GetOperand (Pair, Index));
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}
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