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[RISCV] Add GetVTypeMinimalPredicates for the operation supported by zvfhmin. NFC. (#143847)
This patch adds a new `GetVTypeMinimalPredicates` for `f16` operation supported by `Zvfhmin`. Split the type predicates for minimal support and full compute support. This is a refactor patch for implementing vector compute support for bf16 (Zvfbfa), that we can check `bf16` type whether with `Zvfbfa` extension in `GetVTypePredicates`.
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‎llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td

Lines changed: 36 additions & 32 deletions
Original file line numberDiff line numberDiff line change
@@ -783,6 +783,15 @@ class GetVTypePredicates<VTypeInfo vti> {
783783
true : [HasVInstructions]);
784784
}
785785

786+
class GetVTypeMinimalPredicates<VTypeInfo vti> {
787+
list<Predicate> Predicates = !cond(!eq(vti.Scalar, f16) : [HasVInstructionsF16Minimal],
788+
!eq(vti.Scalar, bf16) : [HasVInstructionsBF16Minimal],
789+
!eq(vti.Scalar, f32) : [HasVInstructionsAnyF],
790+
!eq(vti.Scalar, f64) : [HasVInstructionsF64],
791+
!eq(vti.SEW, 64) : [HasVInstructionsI64],
792+
true : [HasVInstructions]);
793+
}
794+
786795
class VPseudoUSLoadNoMask<VReg RetClass,
787796
int EEW,
788797
DAGOperand sewop = sew> :
@@ -4568,7 +4577,7 @@ multiclass VPatUnaryS_M<string intrinsic_name,
45684577
multiclass VPatUnaryV_V_AnyMask<string intrinsic, string instruction,
45694578
list<VTypeInfo> vtilist> {
45704579
foreach vti = vtilist in {
4571-
let Predicates = GetVTypePredicates<vti>.Predicates in
4580+
let Predicates = GetVTypeMinimalPredicates<vti>.Predicates in
45724581
def : VPatUnaryAnyMask<intrinsic, instruction, "VM",
45734582
vti.Vector, vti.Vector, vti.Mask,
45744583
vti.Log2SEW, vti.LMul, vti.RegClass, vti.RegClass>;
@@ -4887,7 +4896,7 @@ multiclass VPatBinaryV_VV_INT<string intrinsic, string instruction,
48874896
list<VTypeInfo> vtilist> {
48884897
foreach vti = vtilist in {
48894898
defvar ivti = GetIntVTypeInfo<vti>.Vti;
4890-
let Predicates = GetVTypePredicates<vti>.Predicates in
4899+
let Predicates = GetVTypeMinimalPredicates<vti>.Predicates in
48914900
defm : VPatBinary<intrinsic,
48924901
instruction # "_VV_" # vti.LMul.MX # "_E" # vti.SEW,
48934902
vti.Vector, vti.Vector, ivti.Vector, vti.Mask,
@@ -4950,7 +4959,7 @@ multiclass VPatBinaryV_VX_RM<string intrinsic, string instruction,
49504959
multiclass VPatBinaryV_VX_INT<string intrinsic, string instruction,
49514960
list<VTypeInfo> vtilist> {
49524961
foreach vti = vtilist in
4953-
let Predicates = GetVTypePredicates<vti>.Predicates in
4962+
let Predicates = GetVTypeMinimalPredicates<vti>.Predicates in
49544963
defm : VPatBinary<intrinsic, instruction # "_VX_" # vti.LMul.MX,
49554964
vti.Vector, vti.Vector, XLenVT, vti.Mask,
49564965
vti.Log2SEW, vti.RegClass,
@@ -4979,6 +4988,16 @@ multiclass VPatBinaryV_VI_RM<string intrinsic, string instruction,
49794988
vti.RegClass, imm_type>;
49804989
}
49814990

4991+
multiclass VPatBinaryV_VI_INT<string intrinsic, string instruction,
4992+
list<VTypeInfo> vtilist, Operand imm_type> {
4993+
foreach vti = vtilist in
4994+
let Predicates = GetVTypeMinimalPredicates<vti>.Predicates in
4995+
defm : VPatBinary<intrinsic, instruction # "_VI_" # vti.LMul.MX,
4996+
vti.Vector, vti.Vector, XLenVT, vti.Mask,
4997+
vti.Log2SEW, vti.RegClass,
4998+
vti.RegClass, imm_type>;
4999+
}
5000+
49825001
multiclass VPatBinaryM_MM<string intrinsic, string instruction> {
49835002
foreach mti = AllMasks in
49845003
let Predicates = [HasVInstructions] in
@@ -5709,7 +5728,7 @@ multiclass VPatBinaryV_VV_VX_VI_INT<string intrinsic, string instruction,
57095728
list<VTypeInfo> vtilist, Operand ImmType>
57105729
: VPatBinaryV_VV_INT<intrinsic#"_vv", instruction, vtilist>,
57115730
VPatBinaryV_VX_INT<intrinsic#"_vx", instruction, vtilist>,
5712-
VPatBinaryV_VI<intrinsic#"_vx", instruction, vtilist, ImmType>;
5731+
VPatBinaryV_VI_INT<intrinsic#"_vx", instruction, vtilist, ImmType>;
57135732

57145733
multiclass VPatReductionV_VS<string intrinsic, string instruction, bit IsFloat = 0> {
57155734
foreach vti = !if(IsFloat, NoGroupFloatVectors, NoGroupIntegerVectors) in {
@@ -5887,12 +5906,11 @@ multiclass VPatConversionWF_VF<string intrinsic, string instruction,
58875906
defvar fvti = fvtiToFWti.Vti;
58885907
defvar fwti = fvtiToFWti.Wti;
58895908
// Define vfwcvt.f.f.v for f16 when Zvfhmin is enable.
5890-
let Predicates = !if(!eq(fvti.Scalar, f16), [HasVInstructionsF16Minimal],
5891-
!listconcat(GetVTypePredicates<fvti>.Predicates,
5892-
GetVTypePredicates<fwti>.Predicates)) in
5893-
defm : VPatConversion<intrinsic, instruction, "V",
5894-
fwti.Vector, fvti.Vector, fwti.Mask, fvti.Log2SEW,
5895-
fvti.LMul, fwti.RegClass, fvti.RegClass, isSEWAware>;
5909+
let Predicates = !listconcat(GetVTypeMinimalPredicates<fvti>.Predicates,
5910+
GetVTypeMinimalPredicates<fwti>.Predicates) in
5911+
defm : VPatConversion<intrinsic, instruction, "V",
5912+
fwti.Vector, fvti.Vector, fwti.Mask, fvti.Log2SEW,
5913+
fvti.LMul, fwti.RegClass, fvti.RegClass, isSEWAware>;
58965914
}
58975915
}
58985916

@@ -5979,8 +5997,9 @@ multiclass VPatConversionVF_WF_RM<string intrinsic, string instruction,
59795997
foreach fvtiToFWti = wlist in {
59805998
defvar fvti = fvtiToFWti.Vti;
59815999
defvar fwti = fvtiToFWti.Wti;
5982-
let Predicates = !listconcat(GetVTypePredicates<fvti>.Predicates,
5983-
GetVTypePredicates<fwti>.Predicates) in
6000+
// Define vfncvt.f.f.w for f16 when Zvfhmin is enable.
6001+
let Predicates = !listconcat(GetVTypeMinimalPredicates<fvti>.Predicates,
6002+
GetVTypeMinimalPredicates<fwti>.Predicates) in
59846003
defm : VPatConversionRoundingMode<intrinsic, instruction, "W",
59856004
fvti.Vector, fwti.Vector, fvti.Mask, fvti.Log2SEW,
59866005
fvti.LMul, fvti.RegClass, fwti.RegClass,
@@ -6999,8 +7018,7 @@ defm : VPatBinaryV_VM_XM_IM<"int_riscv_vmerge", "PseudoVMERGE">;
69997018
// 11.16. Vector Integer Move Instructions
70007019
//===----------------------------------------------------------------------===//
70017020
foreach vti = AllVectors in {
7002-
let Predicates = !if(!eq(vti.Scalar, f16), [HasVInstructionsF16Minimal],
7003-
GetVTypePredicates<vti>.Predicates) in {
7021+
let Predicates = GetVTypeMinimalPredicates<vti>.Predicates in {
70047022
def : Pat<(vti.Vector (int_riscv_vmv_v_v (vti.Vector vti.RegClass:$passthru),
70057023
(vti.Vector vti.RegClass:$rs1),
70067024
VLOpFrag)),
@@ -7195,8 +7213,7 @@ defm : VPatConversionVI_VF<"int_riscv_vfclass", "PseudoVFCLASS">;
71957213
// NOTE: Clang previously used int_riscv_vfmerge for vector-vector, but now uses
71967214
// int_riscv_vmerge. Support both for compatibility.
71977215
foreach vti = AllFloatVectors in {
7198-
let Predicates = !if(!eq(vti.Scalar, f16), [HasVInstructionsF16Minimal],
7199-
GetVTypePredicates<vti>.Predicates) in
7216+
let Predicates = GetVTypeMinimalPredicates<vti>.Predicates in
72007217
defm : VPatBinaryCarryInTAIL<"int_riscv_vmerge", "PseudoVMERGE", "VVM",
72017218
vti.Vector,
72027219
vti.Vector, vti.Vector, vti.Mask,
@@ -7275,16 +7292,8 @@ defm : VPatConversionVF_WI_RM<"int_riscv_vfncvt_f_xu_w", "PseudoVFNCVT_F_XU",
72757292
isSEWAware=1>;
72767293
defm : VPatConversionVF_WI_RM<"int_riscv_vfncvt_f_x_w", "PseudoVFNCVT_F_X",
72777294
isSEWAware=1>;
7278-
defvar WidenableFloatVectorsExceptF16 = !filter(fvtiToFWti, AllWidenableFloatVectors,
7279-
!ne(fvtiToFWti.Vti.Scalar, f16));
7280-
defm : VPatConversionVF_WF_RM<"int_riscv_vfncvt_f_f_w", "PseudoVFNCVT_F_F",
7281-
WidenableFloatVectorsExceptF16, isSEWAware=1>;
7282-
// Define vfncvt.f.f.w for f16 when Zvfhmin is enable.
7283-
defvar F16WidenableFloatVectors = !filter(fvtiToFWti, AllWidenableFloatVectors,
7284-
!eq(fvtiToFWti.Vti.Scalar, f16));
7285-
let Predicates = [HasVInstructionsF16Minimal] in
72867295
defm : VPatConversionVF_WF_RM<"int_riscv_vfncvt_f_f_w", "PseudoVFNCVT_F_F",
7287-
F16WidenableFloatVectors, isSEWAware=1>;
7296+
AllWidenableFloatVectors, isSEWAware=1>;
72887297
defm : VPatConversionVF_WF_BF_RM<"int_riscv_vfncvtbf16_f_f_w",
72897298
"PseudoVFNCVTBF16_F_F", isSEWAware=1>;
72907299
defm : VPatConversionVF_WF<"int_riscv_vfncvt_rod_f_f_w", "PseudoVFNCVT_ROD_F_F",
@@ -7419,10 +7428,7 @@ defm : VPatBinaryV_VV_INT_EEW<"int_riscv_vrgatherei16_vv", "PseudoVRGATHEREI16",
74197428
eew=16, vtilist=AllIntegerVectors>;
74207429

74217430
defm : VPatBinaryV_VV_VX_VI_INT<"int_riscv_vrgather", "PseudoVRGATHER",
7422-
AllFloatVectorsExceptFP16, uimm5>;
7423-
let Predicates = [HasVInstructionsF16Minimal] in
7424-
defm : VPatBinaryV_VV_VX_VI_INT<"int_riscv_vrgather", "PseudoVRGATHER",
7425-
AllFP16Vectors, uimm5>;
7431+
AllFloatVectors, uimm5>;
74267432
defm : VPatBinaryV_VV_VX_VI_INT<"int_riscv_vrgather", "PseudoVRGATHER",
74277433
AllBFloatVectors, uimm5>;
74287434
defm : VPatBinaryV_VV_INT_EEW<"int_riscv_vrgatherei16_vv", "PseudoVRGATHEREI16",
@@ -7431,9 +7437,7 @@ defm : VPatBinaryV_VV_INT_EEW<"int_riscv_vrgatherei16_vv", "PseudoVRGATHEREI16",
74317437
// 16.5. Vector Compress Instruction
74327438
//===----------------------------------------------------------------------===//
74337439
defm : VPatUnaryV_V_AnyMask<"int_riscv_vcompress", "PseudoVCOMPRESS", AllIntegerVectors>;
7434-
defm : VPatUnaryV_V_AnyMask<"int_riscv_vcompress", "PseudoVCOMPRESS", AllFloatVectorsExceptFP16>;
7435-
let Predicates = [HasVInstructionsF16Minimal] in
7436-
defm : VPatUnaryV_V_AnyMask<"int_riscv_vcompress", "PseudoVCOMPRESS", AllFP16Vectors>;
7440+
defm : VPatUnaryV_V_AnyMask<"int_riscv_vcompress", "PseudoVCOMPRESS", AllFloatVectors>;
74377441
defm : VPatUnaryV_V_AnyMask<"int_riscv_vcompress", "PseudoVCOMPRESS", AllBFloatVectors>;
74387442

74397443
// Include the non-intrinsic ISel patterns

‎llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td

Lines changed: 3 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -864,8 +864,7 @@ multiclass VPatAVGADD_VV_VX_RM<SDNode vop, int vxrm, string suffix = ""> {
864864

865865
// 7.4. Vector Unit-Stride Instructions
866866
foreach vti = AllVectors in
867-
let Predicates = !if(!eq(vti.Scalar, f16), [HasVInstructionsF16Minimal],
868-
GetVTypePredicates<vti>.Predicates) in
867+
let Predicates = GetVTypeMinimalPredicates<vti>.Predicates in
869868
defm : VPatUSLoadStoreSDNode<vti.Vector, vti.RegClass, vti.Log2SEW, vti.LMul,
870869
vti.AVL, vti.RegClass>;
871870
foreach mti = AllMasks in
@@ -1449,9 +1448,8 @@ defm : VPatNConvertI2FPSDNode_W_RM<any_uint_to_fp, "PseudoVFNCVT_F_XU_W">;
14491448
foreach fvtiToFWti = AllWidenableFloatVectors in {
14501449
defvar fvti = fvtiToFWti.Vti;
14511450
defvar fwti = fvtiToFWti.Wti;
1452-
let Predicates = !if(!eq(fvti.Scalar, f16), [HasVInstructionsF16Minimal],
1453-
!listconcat(GetVTypePredicates<fvti>.Predicates,
1454-
GetVTypePredicates<fwti>.Predicates)) in
1451+
let Predicates = !listconcat(GetVTypeMinimalPredicates<fvti>.Predicates,
1452+
GetVTypeMinimalPredicates<fwti>.Predicates) in
14551453
def : Pat<(fvti.Vector (fpround (fwti.Vector fwti.RegClass:$rs1))),
14561454
(!cast<Instruction>("PseudoVFNCVT_F_F_W_"#fvti.LMul.MX#"_E"#fvti.SEW)
14571455
(fvti.Vector (IMPLICIT_DEF)),

‎llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td

Lines changed: 6 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -2683,9 +2683,9 @@ defm : VPatWConvertI2FPVL_V<any_riscv_sint_to_fp_vl, "PseudoVFWCVT_F_X_V">;
26832683
foreach fvtiToFWti = AllWidenableFloatVectors in {
26842684
defvar fvti = fvtiToFWti.Vti;
26852685
defvar fwti = fvtiToFWti.Wti;
2686-
let Predicates = !if(!eq(fvti.Scalar, f16), [HasVInstructionsF16Minimal],
2687-
!listconcat(GetVTypePredicates<fvti>.Predicates,
2688-
GetVTypePredicates<fwti>.Predicates)) in
2686+
// Define vfwcvt.f.f.v for f16 when Zvfhmin is enable.
2687+
let Predicates = !listconcat(GetVTypeMinimalPredicates<fvti>.Predicates,
2688+
GetVTypeMinimalPredicates<fwti>.Predicates) in
26892689
def : Pat<(fwti.Vector (any_riscv_fpextend_vl
26902690
(fvti.Vector fvti.RegClass:$rs1),
26912691
(fvti.Mask VMV0:$vm),
@@ -2726,10 +2726,9 @@ defm : VPatNConvertI2FP_RM_VL_W<riscv_vfcvt_rm_f_x_vl, "PseudoVFNCVT_F_X_W">;
27262726
foreach fvtiToFWti = AllWidenableFloatVectors in {
27272727
defvar fvti = fvtiToFWti.Vti;
27282728
defvar fwti = fvtiToFWti.Wti;
2729-
// Define vfwcvt.f.f.v for f16 when Zvfhmin is enable.
2730-
let Predicates = !if(!eq(fvti.Scalar, f16), [HasVInstructionsF16Minimal],
2731-
!listconcat(GetVTypePredicates<fvti>.Predicates,
2732-
GetVTypePredicates<fwti>.Predicates)) in {
2729+
// Define vfncvt.f.f.w for f16 when Zvfhmin is enable.
2730+
let Predicates = !listconcat(GetVTypeMinimalPredicates<fvti>.Predicates,
2731+
GetVTypeMinimalPredicates<fwti>.Predicates) in {
27332732
def : Pat<(fvti.Vector (any_riscv_fpround_vl
27342733
(fwti.Vector fwti.RegClass:$rs1),
27352734
(fwti.Mask VMV0:$vm), VLOpFrag)),

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