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tclin914circYuan
tclin914
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circYuan
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[RISCV] Implement intrinsics for XAndesVPackFPH (#140007)
This patch implements clang intrinsic support for XAndesVPackFPH. The document for the intrinsics can be found at: https://github.com/andestech/andes-vector-intrinsic-doc/blob/ast-v5_4_0-release-v5/auto-generated/andes-v5/intrinsic_funcs.adoc#andes-vector-packed-fp16-extensionxandesvpackfph and with policy variants https://github.com/andestech/andes-vector-intrinsic-doc/blob/ast-v5_4_0-release-v5/auto-generated/andes-v5/policy_funcs/intrinsic_funcs.adoc#andes-vector-packed-fp16-extensionxandesvpackfph Co-authored-by: Tony Chuan-Yue Yuan <yuan593@andestech.com>
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‎clang/include/clang/Basic/CMakeLists.txt

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@@ -201,3 +201,12 @@ clang_tablegen(riscv_sifive_vector_builtin_cg.inc -gen-riscv-sifive-vector-built
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clang_tablegen(riscv_sifive_vector_builtin_sema.inc -gen-riscv-sifive-vector-builtin-sema
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SOURCE riscv_sifive_vector.td
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TARGET ClangRISCVSiFiveVectorBuiltinSema)
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clang_tablegen(riscv_andes_vector_builtins.inc -gen-riscv-andes-vector-builtins
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SOURCE riscv_andes_vector.td
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TARGET ClangRISCVAndesVectorBuiltins)
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clang_tablegen(riscv_andes_vector_builtin_cg.inc -gen-riscv-andes-vector-builtin-codegen
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SOURCE riscv_andes_vector.td
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TARGET ClangRISCVAndesVectorBuiltinCG)
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clang_tablegen(riscv_andes_vector_builtin_sema.inc -gen-riscv-andes-vector-builtin-sema
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SOURCE riscv_andes_vector.td
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TARGET ClangRISCVAndesVectorBuiltinSema)

‎clang/include/clang/Basic/TargetBuiltins.h

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@@ -197,6 +197,9 @@ namespace clang {
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FirstSiFiveBuiltin,
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LastRVVBuiltin = FirstSiFiveBuiltin - 1,
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#include "clang/Basic/riscv_sifive_vector_builtins.inc"
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FirstAndesBuiltin,
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LastSiFiveBuiltin = FirstAndesBuiltin - 1,
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#include "clang/Basic/riscv_andes_vector_builtins.inc"
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#undef GET_RISCVV_BUILTIN_ENUMERATORS
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FirstTSBuiltin,
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};

‎clang/include/clang/Basic/riscv_andes_vector.td

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@@ -0,0 +1,83 @@
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//==--- riscv_andes_vector.td - RISC-V Andes Builtin function list --------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the builtins for RISC-V Andes Vector Extension. See:
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//
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// https://github.com/andestech/andes-vector-intrinsic-doc
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//
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//===----------------------------------------------------------------------===//
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include "riscv_vector_common.td"
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//===----------------------------------------------------------------------===//
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// Instruction definitions
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//===----------------------------------------------------------------------===//
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// Andes Vector Packed FP16 Extension (XAndesVPackFPH)
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multiclass RVVFPMAD {
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let Log2LMUL = [-2, -1, 0, 1, 2, 3],
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OverloadedName = NAME in {
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defm NAME : RVVOutOp1BuiltinSet<NAME, "x", [["vf", "v", "vvf"]]>;
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let HasFRMRoundModeOp = true in
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defm NAME : RVVOutOp1BuiltinSet<NAME, "x", [["vf", "v", "vvfu"]]>;
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}
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}
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let RequiredFeatures = ["Xandesvpackfph"],
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UnMaskedPolicyScheme = HasPassthruOperand in {
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let ManualCodegen = [{
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{
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// LLVM intrinsic
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// Unmasked: (passthru, op0, op1, round_mode, vl)
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// Masked: (passthru, vector_in, vector_in/scalar_in, mask, frm, vl, policy)
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SmallVector<llvm::Value*, 7> Operands;
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bool HasMaskedOff = !(
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(IsMasked && (PolicyAttrs & RVV_VTA) && (PolicyAttrs & RVV_VMA)) ||
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(!IsMasked && PolicyAttrs & RVV_VTA));
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bool HasRoundModeOp = IsMasked ?
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(HasMaskedOff ? Ops.size() == 6 : Ops.size() == 5) :
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(HasMaskedOff ? Ops.size() == 5 : Ops.size() == 4);
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unsigned Offset = IsMasked ?
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(HasMaskedOff ? 2 : 1) : (HasMaskedOff ? 1 : 0);
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if (!HasMaskedOff)
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Operands.push_back(llvm::PoisonValue::get(ResultType));
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else
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Operands.push_back(Ops[IsMasked ? 1 : 0]);
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Operands.push_back(Ops[Offset]); // op0
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Operands.push_back(Ops[Offset + 1]); // op1
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if (IsMasked)
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Operands.push_back(Ops[0]); // mask
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if (HasRoundModeOp) {
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Operands.push_back(Ops[Offset + 2]); // frm
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Operands.push_back(Ops[Offset + 3]); // vl
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} else {
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Operands.push_back(ConstantInt::get(Ops[Offset + 2]->getType(), 7)); // frm
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Operands.push_back(Ops[Offset + 2]); // vl
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}
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if (IsMasked)
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Operands.push_back(ConstantInt::get(Ops.back()->getType(), PolicyAttrs));
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IntrinsicTypes = {ResultType, Ops[Offset + 1]->getType(),
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Operands.back()->getType()};
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llvm::Function *F = CGM.getIntrinsic(ID, IntrinsicTypes);
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return Builder.CreateCall(F, Operands, "");
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}
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}] in {
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defm nds_vfpmadt : RVVFPMAD;
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defm nds_vfpmadb : RVVFPMAD;
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}
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}

‎clang/include/clang/Sema/RISCVIntrinsicManager.h

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@@ -24,7 +24,7 @@ class Preprocessor;
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namespace sema {
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class RISCVIntrinsicManager {
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public:
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enum class IntrinsicKind : uint8_t { RVV, SIFIVE_VECTOR };
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enum class IntrinsicKind : uint8_t { RVV, SIFIVE_VECTOR, ANDES_VECTOR };
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virtual ~RISCVIntrinsicManager() = default;
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‎clang/include/clang/Sema/SemaRISCV.h

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@@ -51,6 +51,9 @@ class SemaRISCV : public SemaBase {
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/// Indicate RISC-V SiFive vector builtin functions enabled or not.
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bool DeclareSiFiveVectorBuiltins = false;
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/// Indicate RISC-V Andes vector builtin functions enabled or not.
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bool DeclareAndesVectorBuiltins = false;
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std::unique_ptr<sema::RISCVIntrinsicManager> IntrinsicManager;
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};
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‎clang/include/clang/Support/RISCVVIntrinsicUtils.h

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@@ -489,6 +489,7 @@ class RVVIntrinsic {
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enum RVVRequire {
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RVV_REQ_RV64,
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RVV_REQ_Zvfhmin,
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RVV_REQ_Xandesvpackfph,
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RVV_REQ_Xsfvcp,
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RVV_REQ_Xsfvfnrclipxfqf,
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RVV_REQ_Xsfvfwmaccqqq,

‎clang/lib/Basic/Targets/RISCV.cpp

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@@ -265,13 +265,15 @@ void RISCVTargetInfo::getTargetDefines(const LangOptions &Opts,
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static constexpr int NumRVVBuiltins =
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RISCVVector::FirstSiFiveBuiltin - Builtin::FirstTSBuiltin;
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static constexpr int NumRVVSiFiveBuiltins =
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RISCVVector::FirstTSBuiltin - RISCVVector::FirstSiFiveBuiltin;
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RISCVVector::FirstAndesBuiltin - RISCVVector::FirstSiFiveBuiltin;
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static constexpr int NumRVVAndesBuiltins =
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RISCVVector::FirstTSBuiltin - RISCVVector::FirstAndesBuiltin;
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static constexpr int NumRISCVBuiltins =
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RISCV::LastTSBuiltin - RISCVVector::FirstTSBuiltin;
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static constexpr int NumBuiltins =
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RISCV::LastTSBuiltin - Builtin::FirstTSBuiltin;
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static_assert(NumBuiltins ==
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(NumRVVBuiltins + NumRVVSiFiveBuiltins + NumRISCVBuiltins));
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static_assert(NumBuiltins == (NumRVVBuiltins + NumRVVSiFiveBuiltins +
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NumRVVAndesBuiltins + NumRISCVBuiltins));
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276278
namespace RVV {
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#define GET_RISCVV_BUILTIN_STR_TABLE
@@ -299,6 +301,19 @@ static constexpr std::array<Builtin::Info, NumRVVSiFiveBuiltins> BuiltinInfos =
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};
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} // namespace RVVSiFive
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namespace RVVAndes {
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#define GET_RISCVV_BUILTIN_STR_TABLE
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#include "clang/Basic/riscv_andes_vector_builtins.inc"
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#undef GET_RISCVV_BUILTIN_STR_TABLE
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static constexpr std::array<Builtin::Info, NumRVVAndesBuiltins> BuiltinInfos =
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{
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#define GET_RISCVV_BUILTIN_INFOS
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#include "clang/Basic/riscv_andes_vector_builtins.inc"
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#undef GET_RISCVV_BUILTIN_INFOS
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};
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} // namespace RVVAndes
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#define GET_BUILTIN_STR_TABLE
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#include "clang/Basic/BuiltinsRISCV.inc"
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#undef GET_BUILTIN_STR_TABLE
@@ -315,6 +330,7 @@ RISCVTargetInfo::getTargetBuiltins() const {
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return {
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{&RVV::BuiltinStrings, RVV::BuiltinInfos, "__builtin_rvv_"},
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{&RVVSiFive::BuiltinStrings, RVVSiFive::BuiltinInfos, "__builtin_rvv_"},
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{&RVVAndes::BuiltinStrings, RVVAndes::BuiltinInfos, "__builtin_rvv_"},
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{&BuiltinStrings, BuiltinInfos},
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};
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}

‎clang/lib/CodeGen/TargetBuiltins/RISCV.cpp

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@@ -418,6 +418,9 @@ Value *CodeGenFunction::EmitRISCVBuiltinExpr(unsigned BuiltinID,
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// SiFive Vector builtins are handled from here.
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#include "clang/Basic/riscv_sifive_vector_builtin_cg.inc"
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// Andes Vector builtins are handled from here.
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#include "clang/Basic/riscv_andes_vector_builtin_cg.inc"
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}
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assert(ID != Intrinsic::not_intrinsic);

‎clang/lib/Headers/CMakeLists.txt

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@@ -127,6 +127,7 @@ set(riscv_files
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riscv_crypto.h
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riscv_ntlh.h
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sifive_vector.h
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andes_vector.h
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)
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set(systemz_files

‎clang/lib/Headers/andes_vector.h

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//===----- andes_vector.h - Andes Vector definitions ----------------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#ifndef _ANDES_VECTOR_H_
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#define _ANDES_VECTOR_H_
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#include "riscv_vector.h"
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#pragma clang riscv intrinsic andes_vector
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#endif //_ANDES_VECTOR_H_

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