Full specialization

Author: jurahul

llvm/include/llvm/Target/Target.td

@@ -1137,6 +1137,15 @@ class OptionalDefOperand<ValueType ty, dag OpTypes, dag defaultops>
   let MIOperandInfo = OpTypes;
 }
 
+// InstrDecoderOption - This class is used to provide some options to the
+// TableGen DecoderEmitter backend.
+class InstrDecoderOption<string ty, list<int> bws> {
+  string CPPType = ty;       // C++ type for generating non-templated code.
+  list<int> Bitwidths = bws; // List of bitwidths supported by the above type.
+
+  assert !not(!empty(CPPType)), "CPP type cannot be empty";
+  assert !not(!empty(Bitwidths)), "Bitwidths cannot be empty";
+}
 
 // InstrInfo - This class should only be instantiated once to provide parameters
 // which are global to the target machine.
@@ -1159,24 +1168,16 @@ class InstrInfo {
   // This option is a temporary migration help. It will go away.
   bit guessInstructionProperties = true;
 
-  // These properties, when set, opt into the non-templated variants of
-  // `decodeToMCInst` generated by TableGen DecoderEmitter backend. Using this
-  // option helps reduce the code size of the generated code as compared to the
-  // templated `decodeToMCInst` that is generated by default.
-  // For each index `I`, InsnCPPTypes[I] is a C++ type that will be used to
-  // generate a non-templated `decodeToMCInst`, and InstBitwidths[I] is a list
-  // instruction bitwidth(s) whose decoders will be included in the generated
-  // code.
-  list<string> InsnCPPTypes = [];
-  list<list<int>> InsnBitwidths = [];
-  assert !eq(!size(InsnCPPTypes), !size(InsnBitwidths)),
-     "The InsnCPPTypes and InsnBitwidths lists must be the same length";
-
-  // Make sure the InstCPPTypes, if not empty, does not contain empty strings.
-  assert !or(!empty(InsnCPPTypes), !empty(!filter(e, InsnCPPTypes, !empty(e)))),
-     "Entries in InstCPPTypes cannot be empty";
-
-  // Make sure that InsnBitwidths, if not empty, does not contain empty list.
+  // This is a list of instruction decoder options for this target. When non
+  // empty, it should list all the C++ types and associated bitwidths that this
+  // target intends to use to call the TableGen generated `decodeInstruction`
+  // function. If this list is empty, the decoder emitter will generate
+  // templated code. However, if a target intends to call this function with
+  // more than one `InsnType`, it may be beneficial to provide these decoder
+  // options to generate non-templated form of `decodeInstruction` and
+  // associated helper functions and avoid some code duplication in the
+  // `decodeToMCInst` function.
+  list<InstrDecoderOption> DecoderOptions = [];
 }
 
 // Standard Pseudo Instructions.

llvm/lib/Target/AArch64/AArch64.td

@@ -40,11 +40,7 @@ include "AArch64SchedPredExynos.td"
 include "AArch64SchedPredNeoverse.td"
 include "AArch64Combine.td"
 
-def AArch64InstrInfo : InstrInfo {
-  // Opt-in into non-templated code for instruction decoder.
-  let InsnCPPTypes = ["uint32_t"];
-  let InsnBitwidths = [[32]];
-}
+def AArch64InstrInfo : InstrInfo;
 
 //===----------------------------------------------------------------------===//
 // Named operands for MRS/MSR/TLBI/...

llvm/lib/Target/AMDGPU/AMDGPU.td

@@ -1973,6 +1973,13 @@ def FeatureISAVersion12_Generic: FeatureSet<
 
 def AMDGPUInstrInfo : InstrInfo {
   let guessInstructionProperties = 1;
+
+  // Opt-in into non-templated code for instruction decoder.
+  let DecoderOptions = [
+    InstrDecoderOption<"uint32_t", [32]>,
+    InstrDecoderOption<"uint64_t", [64]>,
+    InstrDecoderOption<"DecoderUInt128", [96, 128]>,
+  ];
 }
 
 def AMDGPUAsmParser : AsmParser {

llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp

@@ -591,7 +591,7 @@ DecodeStatus AMDGPUDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
 
     // Try to decode DPP and SDWA first to solve conflict with VOP1 and VOP2
     // encodings
-    if (isGFX11Plus() && Bytes.size() >= 12 ) {
+    if (isGFX11Plus() && Bytes.size() >= 12) {
       DecoderUInt128 DecW = eat12Bytes(Bytes);
 
       if (isGFX11() &&

llvm/lib/Target/M68k/Disassembler/M68kDisassembler.cpp

@@ -111,13 +111,13 @@ static DecodeStatus DecodeFPCSCRegisterClass(MCInst &Inst, uint64_t RegNo,
 }
 #define DecodeFPICRegisterClass DecodeFPCSCRegisterClass
 
-static DecodeStatus DecodeCCRCRegisterClass(MCInst &Inst, APInt &Insn,
+static DecodeStatus DecodeCCRCRegisterClass(MCInst &Inst, const APInt &Insn,
                                             uint64_t Address,
                                             const void *Decoder) {
   llvm_unreachable("unimplemented");
 }
 
-static DecodeStatus DecodeSRCRegisterClass(MCInst &Inst, APInt &Insn,
+static DecodeStatus DecodeSRCRegisterClass(MCInst &Inst, const APInt &Insn,
                                            uint64_t Address,
                                            const void *Decoder) {
   llvm_unreachable("unimplemented");

llvm/lib/Target/RISCV/RISCV.td

@@ -85,10 +85,6 @@ include "RISCVPfmCounters.td"
 
 def RISCVInstrInfo : InstrInfo {
   let guessInstructionProperties = 0;
-
-  // Opt-in into non-templated code for instruction decoder.
-  let InsnCPPTypes = ["uint64_t"];
-  let InsnBitwidths = [[16, 32, 48]];
 }
 
 def RISCVAsmParser : AsmParser {