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[RISCV] Add scheduling info for XSfvqmaccdod/qoq and XSfvfwmaccqqq instructions (#147626)
XSfvqmaccdod/qoq and XSfvfwmaccqqq are SiFive's small-size matrix multiplication extensions. This patches add scheduling info for their instructions along with six new SchedReadWrite.
1 parent 080ade0 commit c2a818f

21 files changed

+472
-2
lines changed

‎llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td

Lines changed: 21 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -167,10 +167,25 @@ multiclass CustomSiFiveVCIX<string suffix, VCIXType type,
167167
InTyRs1, 1>;
168168
}
169169

170+
// For XSfvqmaccdod/qoq and XSfvfwmaccqqq
171+
class SiFiveVMACCScheds<string name> {
172+
defvar n = !tolower(name);
173+
defvar prefix = !if(!ne(!find(n, "fw"), -1), "FW", "Q");
174+
defvar suffix = !if(!ne(!find(n, "2x8x2"), -1), "DOD",
175+
!if(!eq(prefix, "Q"), "QOQ", "QQQ"));
176+
177+
string read = "ReadSF_V" # prefix # "MACC_" # suffix;
178+
string write = "WriteSF_V" # prefix # "MACC_" # suffix;
179+
}
180+
170181
let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
171182
class CustomSiFiveVMACC<bits<6> funct6, RISCVVFormat opv, string opcodestr>
172183
: RVInstVCCustom2<funct6{5-2}, opv.Value, (outs VR:$rd), (ins VR:$rs1, VR:$rs2),
173-
opcodestr, "$rd, $rs1, $rs2"> {
184+
opcodestr, "$rd, $rs1, $rs2">,
185+
SchedTernaryMC<SiFiveVMACCScheds<NAME>.write,
186+
SiFiveVMACCScheds<NAME>.read,
187+
SiFiveVMACCScheds<NAME>.read,
188+
SiFiveVMACCScheds<NAME>.read> {
174189
let vm = 1;
175190
let funct6_lo2 = funct6{1-0};
176191
}
@@ -374,9 +389,13 @@ multiclass VPseudoVC_XVW<LMULInfo m, DAGOperand RS1Class,
374389
}
375390

376391
multiclass VPseudoSiFiveVMACC<string mx, VReg vd_type, VReg vs2_type> {
392+
defvar SchedWriteName = SiFiveVMACCScheds<NAME>.write;
393+
defvar SchedReadName = SiFiveVMACCScheds<NAME>.read;
377394
def "Pseudo" # NAME # "_" # mx
378395
: VPseudoTernaryNoMaskWithPolicy<vd_type, V_M1.vrclass, vs2_type,
379-
"@earlyclobber $rd">;
396+
"@earlyclobber $rd">,
397+
SchedTernary<SchedWriteName, SchedReadName, SchedReadName,
398+
SchedReadName, mx>;
380399
}
381400

382401
multiclass VPseudoSiFiveVQMACCDOD {

‎llvm/lib/Target/RISCV/RISCVSchedAndes45.td

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -332,6 +332,9 @@ defm : UnsupportedSchedSFB;
332332
defm : UnsupportedSchedV;
333333
defm : UnsupportedSchedXsfvcp;
334334
defm : UnsupportedSchedXSfvfnrclipxfqf;
335+
defm : UnsupportedSchedXSfvfwmaccqqq;
336+
defm : UnsupportedSchedXSfvqmaccdod;
337+
defm : UnsupportedSchedXSfvqmaccqoq;
335338
defm : UnsupportedSchedZabha;
336339
defm : UnsupportedSchedZbkb;
337340
defm : UnsupportedSchedZbkx;

‎llvm/lib/Target/RISCV/RISCVSchedGenericOOO.td

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -499,4 +499,7 @@ defm : UnsupportedSchedZvk;
499499
defm : UnsupportedSchedSFB;
500500
defm : UnsupportedSchedXsfvcp;
501501
defm : UnsupportedSchedXSfvfnrclipxfqf;
502+
defm : UnsupportedSchedXSfvfwmaccqqq;
503+
defm : UnsupportedSchedXSfvqmaccdod;
504+
defm : UnsupportedSchedXSfvqmaccqoq;
502505
}

‎llvm/lib/Target/RISCV/RISCVSchedMIPSP8700.td

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -275,5 +275,8 @@ defm : UnsupportedSchedSFB;
275275
defm : UnsupportedSchedZabha;
276276
defm : UnsupportedSchedXsfvcp;
277277
defm : UnsupportedSchedXSfvfnrclipxfqf;
278+
defm : UnsupportedSchedXSfvfwmaccqqq;
279+
defm : UnsupportedSchedXSfvqmaccdod;
280+
defm : UnsupportedSchedXSfvqmaccqoq;
278281
defm : UnsupportedSchedZvk;
279282
}

‎llvm/lib/Target/RISCV/RISCVSchedRocket.td

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -264,5 +264,8 @@ defm : UnsupportedSchedZfhmin;
264264
defm : UnsupportedSchedSFB;
265265
defm : UnsupportedSchedXsfvcp;
266266
defm : UnsupportedSchedXSfvfnrclipxfqf;
267+
defm : UnsupportedSchedXSfvfwmaccqqq;
268+
defm : UnsupportedSchedXSfvqmaccdod;
269+
defm : UnsupportedSchedXSfvqmaccqoq;
267270
defm : UnsupportedSchedZvk;
268271
}

‎llvm/lib/Target/RISCV/RISCVSchedSiFive7.td

Lines changed: 35 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1072,6 +1072,36 @@ multiclass SiFive7WriteResBase<int VLEN,
10721072
defm : LMULWriteResMX<"WriteSF_VFNRClipV", [VCQ, VA1], mx,
10731073
IsWorstCase=!eq(mx, "M2")>;
10741074
}
1075+
1076+
// XSfvqmaccdod
1077+
foreach mx = ["M1", "M2", "M4", "M8"] in {
1078+
defvar Cycles = SiFive7GetCyclesDefault<mx>.c;
1079+
let Latency = 8,
1080+
AcquireAtCycles = [0, 1],
1081+
ReleaseAtCycles = [1, !add(1, Cycles)] in
1082+
defm : LMULWriteResMX<"WriteSF_VQMACC_DOD", [VCQ, VA1], mx,
1083+
IsWorstCase=!eq(mx, "M8")>;
1084+
}
1085+
1086+
// XSfvqmaccqoq
1087+
foreach mx = ["MF2", "M1", "M2", "M4"] in {
1088+
defvar Cycles = SiFive7GetCyclesDefault<mx>.c;
1089+
let Latency = 8,
1090+
AcquireAtCycles = [0, 1],
1091+
ReleaseAtCycles = [1, !add(1, Cycles)] in
1092+
defm : LMULWriteResMX<"WriteSF_VQMACC_QOQ", [VCQ, VA1], mx,
1093+
IsWorstCase=!eq(mx, "M4")>;
1094+
}
1095+
1096+
// XSfvfwmaccqqq
1097+
foreach mx = SchedMxListFW in {
1098+
defvar Cycles = SiFive7GetCyclesDefault<mx>.c;
1099+
defvar IsWorstCase = SiFive7IsWorstCaseMX<mx, SchedMxListFW>.c;
1100+
let Latency = 8,
1101+
AcquireAtCycles = [0, 1],
1102+
ReleaseAtCycles = [1, !add(1, Cycles)] in
1103+
defm : LMULWriteResMX<"WriteSF_VFWMACC_QQQ", [VCQ, VA1], mx, IsWorstCase>;
1104+
}
10751105
}
10761106

10771107
//===----------------------------------------------------------------------===//
@@ -1353,6 +1383,11 @@ multiclass SiFive7ReadAdvance {
13531383
defm : LMULReadAdvance<"ReadSF_VFNRClipV", 0>;
13541384
defm : LMULReadAdvance<"ReadSF_VFNRClipF", 0>;
13551385

1386+
// SiFive VMACC
1387+
defm : LMULReadAdvance<"ReadSF_VQMACC_DOD", 0>;
1388+
defm : LMULReadAdvance<"ReadSF_VQMACC_QOQ", 0>;
1389+
defm : LMULReadAdvance<"ReadSF_VFWMACC_QQQ", 0>;
1390+
13561391
// Others
13571392
def : ReadAdvance<ReadVMask, 0>;
13581393
def : ReadAdvance<ReadVPassthru_WorstCase, 0>;

‎llvm/lib/Target/RISCV/RISCVSchedSiFiveP400.td

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1240,4 +1240,7 @@ defm : UnsupportedSchedSFB;
12401240
defm : UnsupportedSchedZfa;
12411241
defm : UnsupportedSchedXsfvcp;
12421242
defm : UnsupportedSchedXSfvfnrclipxfqf;
1243+
defm : UnsupportedSchedXSfvfwmaccqqq;
1244+
defm : UnsupportedSchedXSfvqmaccdod;
1245+
defm : UnsupportedSchedXSfvqmaccqoq;
12431246
}

‎llvm/lib/Target/RISCV/RISCVSchedSiFiveP500.td

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -360,4 +360,7 @@ defm : UnsupportedSchedZfa;
360360
defm : UnsupportedSchedZvk;
361361
defm : UnsupportedSchedXsfvcp;
362362
defm : UnsupportedSchedXSfvfnrclipxfqf;
363+
defm : UnsupportedSchedXSfvfwmaccqqq;
364+
defm : UnsupportedSchedXSfvqmaccdod;
365+
defm : UnsupportedSchedXSfvqmaccqoq;
363366
}

‎llvm/lib/Target/RISCV/RISCVSchedSiFiveP600.td

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1496,4 +1496,7 @@ defm : UnsupportedSchedSFB;
14961496
defm : UnsupportedSchedZfa;
14971497
defm : UnsupportedSchedXsfvcp;
14981498
defm : UnsupportedSchedXSfvfnrclipxfqf;
1499+
defm : UnsupportedSchedXSfvfwmaccqqq;
1500+
defm : UnsupportedSchedXSfvqmaccdod;
1501+
defm : UnsupportedSchedXSfvqmaccqoq;
14991502
}

‎llvm/lib/Target/RISCV/RISCVSchedSiFiveP800.td

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1185,4 +1185,7 @@ defm : UnsupportedSchedSFB;
11851185
defm : UnsupportedSchedZfaWithQ;
11861186
defm : UnsupportedSchedXsfvcp;
11871187
defm : UnsupportedSchedXSfvfnrclipxfqf;
1188+
defm : UnsupportedSchedXSfvfwmaccqqq;
1189+
defm : UnsupportedSchedXSfvqmaccdod;
1190+
defm : UnsupportedSchedXSfvqmaccqoq;
11881191
}

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