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X86: Replace deprecated FK_PCRel_ with FK_Data_ fixup and PCRel flag
We will unify the generic fixup kinds FK_Data_ and FK_PCRel_. A FK_PCRel_ kind is essentially the corresponding FK_Data_ fixup with the PCRel flag set.
1 parent 22c590b commit c203791

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7 files changed

+72
-82
lines changed

7 files changed

+72
-82
lines changed

‎llvm/lib/MC/MCAsmStreamer.cpp

Lines changed: 8 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -2414,9 +2414,14 @@ void MCAsmStreamer::AddEncodingComment(const MCInst &Inst,
24142414
auto Kind = F.getKind();
24152415
if (mc::isRelocation(Kind))
24162416
OS << ", relocation type: " << Kind;
2417-
else
2418-
OS << ", kind: "
2419-
<< getAssembler().getBackend().getFixupKindInfo(Kind).Name;
2417+
else {
2418+
OS << ", kind: ";
2419+
auto Info = getAssembler().getBackend().getFixupKindInfo(Kind);
2420+
if (F.isPCRel() && StringRef(Info.Name).starts_with("FK_Data_"))
2421+
OS << "FK_PCRel_" << (Info.TargetSize / 8);
2422+
else
2423+
OS << Info.Name;
2424+
}
24202425
OS << '\n';
24212426
}
24222427
}

‎llvm/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp

Lines changed: 0 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -657,15 +657,12 @@ static unsigned getFixupKindSize(unsigned Kind) {
657657
llvm_unreachable("invalid fixup kind!");
658658
case FK_NONE:
659659
return 0;
660-
case FK_PCRel_1:
661660
case FK_SecRel_1:
662661
case FK_Data_1:
663662
return 1;
664-
case FK_PCRel_2:
665663
case FK_SecRel_2:
666664
case FK_Data_2:
667665
return 2;
668-
case FK_PCRel_4:
669666
case X86::reloc_riprel_4byte:
670667
case X86::reloc_riprel_4byte_relax:
671668
case X86::reloc_riprel_4byte_relax_rex:
@@ -680,7 +677,6 @@ static unsigned getFixupKindSize(unsigned Kind) {
680677
case FK_SecRel_4:
681678
case FK_Data_4:
682679
return 4;
683-
case FK_PCRel_8:
684680
case FK_SecRel_8:
685681
case FK_Data_8:
686682
return 8;

‎llvm/lib/Target/X86/MCTargetDesc/X86ELFObjectWriter.cpp

Lines changed: 0 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -76,7 +76,6 @@ static X86_64RelType getType64(MCFixupKind Kind, X86::Specifier &Specifier,
7676
IsPCRel = true;
7777
return RT64_32;
7878
case FK_Data_4:
79-
case FK_PCRel_4:
8079
case X86::reloc_riprel_4byte:
8180
case X86::reloc_riprel_4byte_relax:
8281
case X86::reloc_riprel_4byte_relax_rex:
@@ -88,10 +87,8 @@ static X86_64RelType getType64(MCFixupKind Kind, X86::Specifier &Specifier,
8887
case X86::reloc_branch_4byte_pcrel:
8988
Specifier = X86::S_PLT;
9089
return RT64_32;
91-
case FK_PCRel_2:
9290
case FK_Data_2:
9391
return RT64_16;
94-
case FK_PCRel_1:
9592
case FK_Data_1:
9693
return RT64_8;
9794
}

‎llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp

Lines changed: 51 additions & 63 deletions
Original file line numberDiff line numberDiff line change
@@ -358,8 +358,8 @@ class X86MCCodeEmitter : public MCCodeEmitter {
358358

359359
unsigned getX86RegEncoding(const MCInst &MI, unsigned OpNum) const;
360360

361-
void emitImmediate(const MCOperand &Disp, SMLoc Loc, unsigned ImmSize,
362-
unsigned FixupKind, uint64_t StartByte,
361+
void emitImmediate(const MCOperand &Disp, SMLoc Loc, unsigned FixupKind,
362+
bool IsPCRel, uint64_t StartByte,
363363
SmallVectorImpl<char> &CB,
364364
SmallVectorImpl<MCFixup> &Fixups, int ImmOffset = 0) const;
365365

@@ -441,8 +441,6 @@ static bool isDispOrCDisp8(uint64_t TSFlags, int Value, int &ImmOffset) {
441441
/// instruction with the specified TSFlags.
442442
static MCFixupKind getImmFixupKind(uint64_t TSFlags) {
443443
unsigned Size = X86II::getSizeOfImm(TSFlags);
444-
bool isPCRel = X86II::isImmPCRel(TSFlags);
445-
446444
if (X86II::isImmSigned(TSFlags)) {
447445
switch (Size) {
448446
default:
@@ -455,13 +453,13 @@ static MCFixupKind getImmFixupKind(uint64_t TSFlags) {
455453
default:
456454
llvm_unreachable("Invalid generic fixup size!");
457455
case 1:
458-
return isPCRel ? FK_PCRel_1 : FK_Data_1;
456+
return FK_Data_1;
459457
case 2:
460-
return isPCRel ? FK_PCRel_2 : FK_Data_2;
458+
return FK_Data_2;
461459
case 4:
462-
return isPCRel ? FK_PCRel_4 : FK_Data_4;
460+
return FK_Data_4;
463461
case 8:
464-
return isPCRel ? FK_PCRel_8 : FK_Data_8;
462+
return FK_Data_8;
465463
}
466464
}
467465

@@ -506,7 +504,8 @@ static bool isPCRel32Branch(const MCInst &MI, const MCInstrInfo &MCII) {
506504
const MCInstrDesc &Desc = MCII.get(Opcode);
507505
if ((Opcode != X86::CALL64pcrel32 && Opcode != X86::JMP_4 &&
508506
Opcode != X86::JCC_4) ||
509-
getImmFixupKind(Desc.TSFlags) != FK_PCRel_4)
507+
!(getImmFixupKind(Desc.TSFlags) == FK_Data_4 &&
508+
X86II::isImmPCRel(Desc.TSFlags)))
510509
return false;
511510

512511
unsigned CurOp = X86II::getOperandBias(Desc);
@@ -528,17 +527,29 @@ unsigned X86MCCodeEmitter::getX86RegEncoding(const MCInst &MI,
528527
}
529528

530529
void X86MCCodeEmitter::emitImmediate(const MCOperand &DispOp, SMLoc Loc,
531-
unsigned Size, unsigned FixupKind,
530+
unsigned FixupKind, bool PCRel,
532531
uint64_t StartByte,
533532
SmallVectorImpl<char> &CB,
534533
SmallVectorImpl<MCFixup> &Fixups,
535534
int ImmOffset) const {
535+
unsigned Size = 4;
536+
switch (FixupKind) {
537+
case FK_Data_1:
538+
Size = 1;
539+
break;
540+
case FK_Data_2:
541+
Size = 2;
542+
break;
543+
case FK_Data_8:
544+
Size = 8;
545+
break;
546+
}
536547
const MCExpr *Expr = nullptr;
537548
if (DispOp.isImm()) {
538549
// If this is a simple integer displacement that doesn't require a
539550
// relocation, emit it now.
540-
if (FixupKind != FK_PCRel_1 && FixupKind != FK_PCRel_2 &&
541-
FixupKind != FK_PCRel_4) {
551+
if (!(is_contained({FK_Data_1, FK_Data_2, FK_Data_4}, FixupKind) &&
552+
PCRel)) {
542553
emitConstant(DispOp.getImm() + ImmOffset, Size, CB);
543554
return;
544555
}
@@ -578,33 +589,13 @@ void X86MCCodeEmitter::emitImmediate(const MCOperand &DispOp, SMLoc Loc,
578589

579590
// If the fixup is pc-relative, we need to bias the value to be relative to
580591
// the start of the field, not the end of the field.
581-
bool PCRel = false;
582-
switch (FixupKind) {
583-
case FK_PCRel_1:
584-
PCRel = true;
585-
ImmOffset -= 1;
586-
break;
587-
case FK_PCRel_2:
588-
PCRel = true;
589-
ImmOffset -= 2;
590-
break;
591-
case FK_PCRel_4:
592-
case X86::reloc_riprel_4byte:
593-
case X86::reloc_riprel_4byte_movq_load:
594-
case X86::reloc_riprel_4byte_movq_load_rex2:
595-
case X86::reloc_riprel_4byte_relax:
596-
case X86::reloc_riprel_4byte_relax_rex:
597-
case X86::reloc_riprel_4byte_relax_rex2:
598-
case X86::reloc_branch_4byte_pcrel:
599-
case X86::reloc_riprel_4byte_relax_evex:
600-
PCRel = true;
601-
ImmOffset -= 4;
592+
if (PCRel) {
593+
ImmOffset -= Size;
602594
// If this is a pc-relative load off _GLOBAL_OFFSET_TABLE_:
603595
// leaq _GLOBAL_OFFSET_TABLE_(%rip), %r15
604596
// this needs to be a GOTPC32 relocation.
605-
if (startsWithGlobalOffsetTable(Expr) != GOT_None)
597+
if (Size == 4 && startsWithGlobalOffsetTable(Expr) != GOT_None)
606598
FixupKind = X86::reloc_global_offset_table;
607-
break;
608599
}
609600

610601
if (ImmOffset)
@@ -712,8 +703,8 @@ void X86MCCodeEmitter::emitMemModRMByte(
712703
? X86II::getSizeOfImm(TSFlags)
713704
: 0;
714705

715-
emitImmediate(Disp, MI.getLoc(), 4, MCFixupKind(FixupKind), StartByte, CB,
716-
Fixups, -ImmSize);
706+
emitImmediate(Disp, MI.getLoc(), FixupKind, true, StartByte, CB, Fixups,
707+
-ImmSize);
717708
return;
718709
}
719710

@@ -767,7 +758,8 @@ void X86MCCodeEmitter::emitMemModRMByte(
767758
}
768759
// Use the [REG]+disp8 form, including for [BP] which cannot be encoded.
769760
emitByte(modRMByte(1, RegOpcodeField, RMfield), CB);
770-
emitImmediate(Disp, MI.getLoc(), 1, FK_Data_1, StartByte, CB, Fixups);
761+
emitImmediate(Disp, MI.getLoc(), FK_Data_1, false, StartByte, CB,
762+
Fixups);
771763
return;
772764
}
773765
// This is the [REG]+disp16 case.
@@ -779,7 +771,7 @@ void X86MCCodeEmitter::emitMemModRMByte(
779771
}
780772

781773
// Emit 16-bit displacement for plain disp16 or [REG]+disp16 cases.
782-
emitImmediate(Disp, MI.getLoc(), 2, FK_Data_2, StartByte, CB, Fixups);
774+
emitImmediate(Disp, MI.getLoc(), FK_Data_2, false, StartByte, CB, Fixups);
783775
return;
784776
}
785777

@@ -797,7 +789,7 @@ void X86MCCodeEmitter::emitMemModRMByte(
797789
STI.hasFeature(X86::Is64Bit))) {
798790
if (!BaseReg) { // [disp32] in X86-32 mode
799791
emitByte(modRMByte(0, RegOpcodeField, 5), CB);
800-
emitImmediate(Disp, MI.getLoc(), 4, FK_Data_4, StartByte, CB, Fixups);
792+
emitImmediate(Disp, MI.getLoc(), FK_Data_4, false, StartByte, CB, Fixups);
801793
return;
802794
}
803795

@@ -833,8 +825,8 @@ void X86MCCodeEmitter::emitMemModRMByte(
833825
int ImmOffset = 0;
834826
if (isDispOrCDisp8(TSFlags, Disp.getImm(), ImmOffset)) {
835827
emitByte(modRMByte(1, RegOpcodeField, BaseRegNo), CB);
836-
emitImmediate(Disp, MI.getLoc(), 1, FK_Data_1, StartByte, CB, Fixups,
837-
ImmOffset);
828+
emitImmediate(Disp, MI.getLoc(), FK_Data_1, false, StartByte, CB,
829+
Fixups, ImmOffset);
838830
return;
839831
}
840832
}
@@ -846,8 +838,8 @@ void X86MCCodeEmitter::emitMemModRMByte(
846838
unsigned Opcode = MI.getOpcode();
847839
unsigned FixupKind = Opcode == X86::MOV32rm ? X86::reloc_signed_4byte_relax
848840
: X86::reloc_signed_4byte;
849-
emitImmediate(Disp, MI.getLoc(), 4, MCFixupKind(FixupKind), StartByte, CB,
850-
Fixups);
841+
emitImmediate(Disp, MI.getLoc(), MCFixupKind(FixupKind), false, StartByte,
842+
CB, Fixups);
851843
return;
852844
}
853845

@@ -895,11 +887,11 @@ void X86MCCodeEmitter::emitMemModRMByte(
895887

896888
// Do we need to output a displacement?
897889
if (ForceDisp8)
898-
emitImmediate(Disp, MI.getLoc(), 1, FK_Data_1, StartByte, CB, Fixups,
890+
emitImmediate(Disp, MI.getLoc(), FK_Data_1, false, StartByte, CB, Fixups,
899891
ImmOffset);
900892
else if (ForceDisp32)
901-
emitImmediate(Disp, MI.getLoc(), 4, MCFixupKind(X86::reloc_signed_4byte),
902-
StartByte, CB, Fixups);
893+
emitImmediate(Disp, MI.getLoc(), MCFixupKind(X86::reloc_signed_4byte),
894+
false, StartByte, CB, Fixups);
903895
}
904896

905897
/// Emit all instruction prefixes.
@@ -1634,33 +1626,29 @@ void X86MCCodeEmitter::encodeInstruction(const MCInst &MI,
16341626
break;
16351627

16361628
const MCOperand &Op = MI.getOperand(CurOp++);
1637-
emitImmediate(Op, MI.getLoc(), X86II::getSizeOfImm(TSFlags),
1638-
MCFixupKind(X86::reloc_branch_4byte_pcrel), StartByte, CB,
1639-
Fixups);
1629+
emitImmediate(Op, MI.getLoc(), MCFixupKind(X86::reloc_branch_4byte_pcrel),
1630+
true, StartByte, CB, Fixups);
16401631
break;
16411632
}
16421633
case X86II::RawFrmMemOffs:
16431634
emitByte(BaseOpcode, CB);
1644-
emitImmediate(MI.getOperand(CurOp++), MI.getLoc(),
1645-
X86II::getSizeOfImm(TSFlags), getImmFixupKind(TSFlags),
1646-
StartByte, CB, Fixups);
1635+
emitImmediate(MI.getOperand(CurOp++), MI.getLoc(), getImmFixupKind(TSFlags),
1636+
X86II::isImmPCRel(TSFlags), StartByte, CB, Fixups);
16471637
++CurOp; // skip segment operand
16481638
break;
16491639
case X86II::RawFrmImm8:
16501640
emitByte(BaseOpcode, CB);
1651-
emitImmediate(MI.getOperand(CurOp++), MI.getLoc(),
1652-
X86II::getSizeOfImm(TSFlags), getImmFixupKind(TSFlags),
1641+
emitImmediate(MI.getOperand(CurOp++), MI.getLoc(), getImmFixupKind(TSFlags),
1642+
X86II::isImmPCRel(TSFlags), StartByte, CB, Fixups);
1643+
emitImmediate(MI.getOperand(CurOp++), MI.getLoc(), FK_Data_1, false,
16531644
StartByte, CB, Fixups);
1654-
emitImmediate(MI.getOperand(CurOp++), MI.getLoc(), 1, FK_Data_1, StartByte,
1655-
CB, Fixups);
16561645
break;
16571646
case X86II::RawFrmImm16:
16581647
emitByte(BaseOpcode, CB);
1659-
emitImmediate(MI.getOperand(CurOp++), MI.getLoc(),
1660-
X86II::getSizeOfImm(TSFlags), getImmFixupKind(TSFlags),
1648+
emitImmediate(MI.getOperand(CurOp++), MI.getLoc(), getImmFixupKind(TSFlags),
1649+
X86II::isImmPCRel(TSFlags), StartByte, CB, Fixups);
1650+
emitImmediate(MI.getOperand(CurOp++), MI.getLoc(), FK_Data_2, false,
16611651
StartByte, CB, Fixups);
1662-
emitImmediate(MI.getOperand(CurOp++), MI.getLoc(), 2, FK_Data_2, StartByte,
1663-
CB, Fixups);
16641652
break;
16651653

16661654
case X86II::AddRegFrm:
@@ -2013,7 +2001,7 @@ void X86MCCodeEmitter::encodeInstruction(const MCInst &MI,
20132001
assert(Val < 16 && "Immediate operand value out of range");
20142002
I8RegNum |= Val;
20152003
}
2016-
emitImmediate(MCOperand::createImm(I8RegNum), MI.getLoc(), 1, FK_Data_1,
2004+
emitImmediate(MCOperand::createImm(I8RegNum), MI.getLoc(), FK_Data_1, false,
20172005
StartByte, CB, Fixups);
20182006
} else {
20192007
// If there is a remaining operand, it must be a trailing immediate. Emit it
@@ -2024,7 +2012,7 @@ void X86MCCodeEmitter::encodeInstruction(const MCInst &MI,
20242012
unsigned RemaningOps = NumOps - CurOp - 2 * HasTwoConditionalOps;
20252013
while (RemaningOps) {
20262014
emitImmediate(MI.getOperand(CurOp++), MI.getLoc(),
2027-
X86II::getSizeOfImm(TSFlags), getImmFixupKind(TSFlags),
2015+
getImmFixupKind(TSFlags), X86II::isImmPCRel(TSFlags),
20282016
StartByte, CB, Fixups);
20292017
--RemaningOps;
20302018
}

‎llvm/lib/Target/X86/MCTargetDesc/X86MachObjectWriter.cpp

Lines changed: 0 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -78,11 +78,8 @@ static unsigned getFixupKindLog2Size(unsigned Kind) {
7878
switch (Kind) {
7979
default:
8080
llvm_unreachable("invalid fixup kind!");
81-
case FK_PCRel_1:
8281
case FK_Data_1: return 0;
83-
case FK_PCRel_2:
8482
case FK_Data_2: return 1;
85-
case FK_PCRel_4:
8683
// FIXME: Remove these!!!
8784
case X86::reloc_riprel_4byte:
8885
case X86::reloc_riprel_4byte_relax:

‎llvm/lib/Target/X86/MCTargetDesc/X86WinCOFFObjectWriter.cpp

Lines changed: 12 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -45,14 +45,17 @@ unsigned X86WinCOFFObjectWriter::getRelocType(MCContext &Ctx,
4545
const MCAsmBackend &MAB) const {
4646
const bool Is64Bit = getMachine() == COFF::IMAGE_FILE_MACHINE_AMD64;
4747
unsigned FixupKind = Fixup.getKind();
48+
bool PCRel = Fixup.isPCRel();
4849
if (IsCrossSection) {
4950
// IMAGE_REL_AMD64_REL64 does not exist. We treat FK_Data_8 as FK_PCRel_4 so
5051
// that .quad a-b can lower to IMAGE_REL_AMD64_REL32. This allows generic
5152
// instrumentation to not bother with the COFF limitation. A negative value
5253
// needs attention.
53-
if (FixupKind == FK_Data_4 || FixupKind == llvm::X86::reloc_signed_4byte ||
54-
(FixupKind == FK_Data_8 && Is64Bit)) {
55-
FixupKind = FK_PCRel_4;
54+
if (!PCRel &&
55+
(FixupKind == FK_Data_4 || FixupKind == llvm::X86::reloc_signed_4byte ||
56+
(FixupKind == FK_Data_8 && Is64Bit))) {
57+
FixupKind = FK_Data_4;
58+
PCRel = true;
5659
} else {
5760
Ctx.reportError(Fixup.getLoc(), "Cannot represent this expression");
5861
return COFF::IMAGE_REL_AMD64_ADDR32;
@@ -62,7 +65,6 @@ unsigned X86WinCOFFObjectWriter::getRelocType(MCContext &Ctx,
6265
auto Spec = Target.getSpecifier();
6366
if (Is64Bit) {
6467
switch (FixupKind) {
65-
case FK_PCRel_4:
6668
case X86::reloc_riprel_4byte:
6769
case X86::reloc_riprel_4byte_movq_load:
6870
case X86::reloc_riprel_4byte_movq_load_rex2:
@@ -73,6 +75,9 @@ unsigned X86WinCOFFObjectWriter::getRelocType(MCContext &Ctx,
7375
case X86::reloc_branch_4byte_pcrel:
7476
return COFF::IMAGE_REL_AMD64_REL32;
7577
case FK_Data_4:
78+
if (PCRel)
79+
return COFF::IMAGE_REL_AMD64_REL32;
80+
[[fallthrough]];
7681
case X86::reloc_signed_4byte:
7782
case X86::reloc_signed_4byte_relax:
7883
if (Spec == MCSymbolRefExpr::VK_COFF_IMGREL32)
@@ -92,11 +97,13 @@ unsigned X86WinCOFFObjectWriter::getRelocType(MCContext &Ctx,
9297
}
9398
} else if (getMachine() == COFF::IMAGE_FILE_MACHINE_I386) {
9499
switch (FixupKind) {
95-
case FK_PCRel_4:
96100
case X86::reloc_riprel_4byte:
97101
case X86::reloc_riprel_4byte_movq_load:
98102
return COFF::IMAGE_REL_I386_REL32;
99103
case FK_Data_4:
104+
if (PCRel)
105+
return COFF::IMAGE_REL_I386_REL32;
106+
[[fallthrough]];
100107
case X86::reloc_signed_4byte:
101108
case X86::reloc_signed_4byte_relax:
102109
if (Spec == MCSymbolRefExpr::VK_COFF_IMGREL32)

‎llvm/test/MC/ELF/mc-dump.s

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -13,7 +13,7 @@
1313
# CHECK-NEXT: Symbol @0 _start
1414
# CHECK-NEXT:0 Org Offset:3 Value:0
1515
# CHECK-NEXT:3 Relaxable Size:2 <MCInst #1996 <MCOperand Expr:.Ltmp0>>
16-
# CHECK-NEXT: Fixup @1 Value:.Ltmp0-1 Kind:4006
16+
# CHECK-NEXT: Fixup @1 Value:.Ltmp0-1 Kind:4001
1717
# CHECK-NEXT:5 Data Size:16 [48,8b,04,25,00,00,00,00,48,8b,04,25,00,00,00,00]
1818
# CHECK-NEXT: Fixup @4 Value:f0@<variant 11> Kind:4021
1919
# CHECK-NEXT: Fixup @12 Value:_start@<variant 11> Kind:4021

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