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[AMDGPU] Add a debug option -amdgpu-snop-padding for GCNHazardRecognizer (#146587)
This can help to identify if there is potential hazards. Co-authored-by: Byrnes, Jeffrey <Jeffrey.Byrnes@amd.com>
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‎llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp

Lines changed: 6 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -44,6 +44,11 @@ static cl::opt<unsigned, false, MFMAPaddingRatioParser>
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cl::desc("Fill a percentage of the latency between "
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"neighboring MFMA with s_nops."));
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// This is intended for debugging purposes only.
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static cl::opt<unsigned>
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NopPadding("amdgpu-snop-padding", cl::init(0), cl::Hidden,
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cl::desc("Insert a s_nop x before every instruction"));
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//===----------------------------------------------------------------------===//
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// Hazard Recognizer Implementation
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//===----------------------------------------------------------------------===//
@@ -300,7 +305,7 @@ unsigned GCNHazardRecognizer::PreEmitNoops(MachineInstr *MI) {
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unsigned W = PreEmitNoopsCommon(MI);
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fixHazards(MI);
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CurrCycleInstr = nullptr;
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return W;
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return std::max(W, NopPadding.getValue());
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}
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unsigned GCNHazardRecognizer::PreEmitNoopsCommon(MachineInstr *MI) {

‎llvm/test/CodeGen/AMDGPU/amdgpu-snop-padding.mir

Lines changed: 132 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,132 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx942 -amdgpu-snop-padding=8 -run-pass post-RA-hazard-rec %s -o - | FileCheck -check-prefix=GCN8 %s
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# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx942 -amdgpu-snop-padding=16 -run-pass post-RA-hazard-rec %s -o - | FileCheck -check-prefix=GCN16 %s
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---
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name: test_snop_padding
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tracksRegLiveness: true
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frameInfo:
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maxAlignment: 4
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stack:
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- { id: 0, type: spill-slot, size: 4, alignment: 4, stack-id: sgpr-spill }
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machineFunctionInfo:
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isEntryFunction: false
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scratchRSrcReg: '$sgpr0_sgpr1_sgpr2_sgpr3'
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stackPtrOffsetReg: '$sgpr32'
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frameOffsetReg: '$sgpr33'
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hasSpilledSGPRs: true
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body: |
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; GCN8-LABEL: name: test_snop_padding
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; GCN8: bb.0:
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; GCN8-NEXT: successors: %bb.1(0x80000000)
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; GCN8-NEXT: liveins: $sgpr6, $sgpr10_sgpr11
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; GCN8-NEXT: {{ $}}
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; GCN8-NEXT: S_NOP 7
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; GCN8-NEXT: S_BRANCH %bb.1
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; GCN8-NEXT: {{ $}}
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; GCN8-NEXT: bb.1:
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; GCN8-NEXT: successors: %bb.3(0x40000000), %bb.2(0x40000000)
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; GCN8-NEXT: liveins: $sgpr6, $sgpr10_sgpr11
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; GCN8-NEXT: {{ $}}
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; GCN8-NEXT: S_NOP 7
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; GCN8-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 10, implicit $exec
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; GCN8-NEXT: S_NOP 7
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; GCN8-NEXT: S_CBRANCH_EXECZ %bb.3, implicit $exec
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; GCN8-NEXT: {{ $}}
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; GCN8-NEXT: bb.2:
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; GCN8-NEXT: successors: %bb.3(0x80000000)
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; GCN8-NEXT: liveins: $sgpr6, $sgpr10_sgpr11
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; GCN8-NEXT: {{ $}}
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; GCN8-NEXT: S_NOP 7
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; GCN8-NEXT: SI_SPILL_S32_SAVE killed $sgpr6, %stack.0, implicit $exec, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr32
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; GCN8-NEXT: S_NOP 7
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; GCN8-NEXT: S_NOP 0
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; GCN8-NEXT: S_NOP 7
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; GCN8-NEXT: renamable $sgpr6 = SI_SPILL_S32_RESTORE %stack.0, implicit $exec, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr32
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; GCN8-NEXT: S_NOP 7
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; GCN8-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 20, implicit $exec
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; GCN8-NEXT: S_NOP 7
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; GCN8-NEXT: S_BRANCH %bb.3
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; GCN8-NEXT: {{ $}}
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; GCN8-NEXT: bb.3:
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; GCN8-NEXT: liveins: $sgpr10_sgpr11
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; GCN8-NEXT: {{ $}}
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; GCN8-NEXT: S_NOP 7
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; GCN8-NEXT: $sgpr5 = V_READFIRSTLANE_B32 [[V_MOV_B32_e32_]], implicit $exec
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; GCN8-NEXT: S_NOP 7
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; GCN8-NEXT: S_STORE_DWORD_IMM $sgpr5, $sgpr10_sgpr11, 0, 0
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; GCN8-NEXT: S_NOP 7
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; GCN8-NEXT: SI_RETURN
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;
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; GCN16-LABEL: name: test_snop_padding
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; GCN16: bb.0:
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; GCN16-NEXT: successors: %bb.1(0x80000000)
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; GCN16-NEXT: liveins: $sgpr6, $sgpr10_sgpr11
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; GCN16-NEXT: {{ $}}
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; GCN16-NEXT: S_NOP 7
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; GCN16-NEXT: S_NOP 7
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; GCN16-NEXT: S_BRANCH %bb.1
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; GCN16-NEXT: {{ $}}
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; GCN16-NEXT: bb.1:
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; GCN16-NEXT: successors: %bb.3(0x40000000), %bb.2(0x40000000)
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; GCN16-NEXT: liveins: $sgpr6, $sgpr10_sgpr11
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; GCN16-NEXT: {{ $}}
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; GCN16-NEXT: S_NOP 7
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; GCN16-NEXT: S_NOP 7
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; GCN16-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 10, implicit $exec
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; GCN16-NEXT: S_NOP 7
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; GCN16-NEXT: S_NOP 7
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; GCN16-NEXT: S_CBRANCH_EXECZ %bb.3, implicit $exec
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; GCN16-NEXT: {{ $}}
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; GCN16-NEXT: bb.2:
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; GCN16-NEXT: successors: %bb.3(0x80000000)
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; GCN16-NEXT: liveins: $sgpr6, $sgpr10_sgpr11
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; GCN16-NEXT: {{ $}}
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; GCN16-NEXT: S_NOP 7
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; GCN16-NEXT: S_NOP 7
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; GCN16-NEXT: SI_SPILL_S32_SAVE killed $sgpr6, %stack.0, implicit $exec, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr32
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; GCN16-NEXT: S_NOP 7
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; GCN16-NEXT: S_NOP 7
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; GCN16-NEXT: S_NOP 0
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; GCN16-NEXT: S_NOP 7
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; GCN16-NEXT: S_NOP 7
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; GCN16-NEXT: renamable $sgpr6 = SI_SPILL_S32_RESTORE %stack.0, implicit $exec, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr32
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; GCN16-NEXT: S_NOP 7
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; GCN16-NEXT: S_NOP 7
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; GCN16-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 20, implicit $exec
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; GCN16-NEXT: S_NOP 7
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; GCN16-NEXT: S_NOP 7
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; GCN16-NEXT: S_BRANCH %bb.3
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; GCN16-NEXT: {{ $}}
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; GCN16-NEXT: bb.3:
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; GCN16-NEXT: liveins: $sgpr10_sgpr11
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; GCN16-NEXT: {{ $}}
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; GCN16-NEXT: S_NOP 7
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; GCN16-NEXT: S_NOP 7
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; GCN16-NEXT: $sgpr5 = V_READFIRSTLANE_B32 [[V_MOV_B32_e32_]], implicit $exec
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; GCN16-NEXT: S_NOP 7
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; GCN16-NEXT: S_NOP 7
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; GCN16-NEXT: S_STORE_DWORD_IMM $sgpr5, $sgpr10_sgpr11, 0, 0
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; GCN16-NEXT: S_NOP 7
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; GCN16-NEXT: S_NOP 7
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; GCN16-NEXT: SI_RETURN
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bb.0:
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liveins: $sgpr6, $sgpr10_sgpr11
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S_BRANCH %bb.1
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bb.1:
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liveins: $sgpr6, $sgpr10_sgpr11
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%0:vgpr_32 = V_MOV_B32_e32 10, implicit $exec
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S_CBRANCH_EXECZ %bb.3, implicit $exec
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bb.2:
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liveins: $sgpr6, $sgpr10_sgpr11
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SI_SPILL_S32_SAVE killed $sgpr6, %stack.0, implicit $exec, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr32
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S_NOP 0
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renamable $sgpr6 = SI_SPILL_S32_RESTORE %stack.0, implicit $exec, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr32
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%0:vgpr_32 = V_MOV_B32_e32 20, implicit $exec
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S_BRANCH %bb.3
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bb.3:
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liveins: $sgpr10_sgpr11
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$sgpr5 = V_READFIRSTLANE_B32 %0:vgpr_32, implicit $exec
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S_STORE_DWORD_IMM $sgpr5, $sgpr10_sgpr11, 0, 0
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SI_RETURN
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...

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