@@ -24086,6 +24086,12 @@ static const Intrinsic::ID FixedVlsegIntrIds[] = {
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Intrinsic::riscv_seg6_load_mask, Intrinsic::riscv_seg7_load_mask,
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Intrinsic::riscv_seg8_load_mask};
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+ static const Intrinsic::ID ScalableVlsegIntrIds[] = {
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+ Intrinsic::riscv_vlseg2_mask, Intrinsic::riscv_vlseg3_mask,
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+ Intrinsic::riscv_vlseg4_mask, Intrinsic::riscv_vlseg5_mask,
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+ Intrinsic::riscv_vlseg6_mask, Intrinsic::riscv_vlseg7_mask,
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+ Intrinsic::riscv_vlseg8_mask};
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+
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/// Lower an interleaved load into a vlsegN intrinsic.
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///
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/// E.g. Lower an interleaved load (Factor = 2):
@@ -24155,6 +24161,12 @@ static const Intrinsic::ID FixedVssegIntrIds[] = {
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Intrinsic::riscv_seg6_store_mask, Intrinsic::riscv_seg7_store_mask,
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Intrinsic::riscv_seg8_store_mask};
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+ static const Intrinsic::ID ScalableVssegIntrIds[] = {
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+ Intrinsic::riscv_vsseg2_mask, Intrinsic::riscv_vsseg3_mask,
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+ Intrinsic::riscv_vsseg4_mask, Intrinsic::riscv_vsseg5_mask,
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+ Intrinsic::riscv_vsseg6_mask, Intrinsic::riscv_vsseg7_mask,
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+ Intrinsic::riscv_vsseg8_mask};
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+
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/// Lower an interleaved store into a vssegN intrinsic.
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///
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/// E.g. Lower an interleaved store (Factor = 3):
@@ -24465,13 +24477,6 @@ bool RISCVTargetLowering::lowerInterleavedVPLoad(
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{FVTy, PtrTy, XLenTy},
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{Load->getArgOperand(0), Mask, EVL});
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} else {
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- static const Intrinsic::ID IntrMaskIds[] = {
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- Intrinsic::riscv_vlseg2_mask, Intrinsic::riscv_vlseg3_mask,
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- Intrinsic::riscv_vlseg4_mask, Intrinsic::riscv_vlseg5_mask,
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- Intrinsic::riscv_vlseg6_mask, Intrinsic::riscv_vlseg7_mask,
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- Intrinsic::riscv_vlseg8_mask,
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- };
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-
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unsigned SEW = DL.getTypeSizeInBits(VTy->getElementType());
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unsigned NumElts = VTy->getElementCount().getKnownMinValue();
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Type *VecTupTy = TargetExtType::get(
@@ -24483,7 +24488,7 @@ bool RISCVTargetLowering::lowerInterleavedVPLoad(
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Value *PoisonVal = PoisonValue::get(VecTupTy);
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Function *VlsegNFunc = Intrinsic::getOrInsertDeclaration(
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- Load->getModule(), IntrMaskIds [Factor - 2],
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+ Load->getModule(), ScalableVlsegIntrIds [Factor - 2],
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{VecTupTy, PtrTy, Mask->getType(), EVL->getType()});
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Value *Operands[] = {
@@ -24583,13 +24588,6 @@ bool RISCVTargetLowering::lowerInterleavedVPStore(
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return true;
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}
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- static const Intrinsic::ID IntrMaskIds[] = {
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- Intrinsic::riscv_vsseg2_mask, Intrinsic::riscv_vsseg3_mask,
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- Intrinsic::riscv_vsseg4_mask, Intrinsic::riscv_vsseg5_mask,
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- Intrinsic::riscv_vsseg6_mask, Intrinsic::riscv_vsseg7_mask,
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- Intrinsic::riscv_vsseg8_mask,
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- };
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-
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unsigned SEW = DL.getTypeSizeInBits(VTy->getElementType());
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unsigned NumElts = VTy->getElementCount().getKnownMinValue();
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Type *VecTupTy = TargetExtType::get(
@@ -24606,7 +24604,7 @@ bool RISCVTargetLowering::lowerInterleavedVPStore(
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VecInsertFunc, {StoredVal, InterleaveOperands[i], Builder.getInt32(i)});
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Function *VssegNFunc = Intrinsic::getOrInsertDeclaration(
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- Store->getModule(), IntrMaskIds [Factor - 2],
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+ Store->getModule(), ScalableVssegIntrIds [Factor - 2],
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{VecTupTy, PtrTy, Mask->getType(), EVL->getType()});
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Value *Operands[] = {StoredVal, Store->getArgOperand(1), Mask, EVL,
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