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[RISCV] Consolidate intrinsic ID tables [nfc]
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+14
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llvm/lib/Target/RISCV/RISCVISelLowering.cpp

Lines changed: 14 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -24086,6 +24086,12 @@ static const Intrinsic::ID FixedVlsegIntrIds[] = {
2408624086
Intrinsic::riscv_seg6_load_mask, Intrinsic::riscv_seg7_load_mask,
2408724087
Intrinsic::riscv_seg8_load_mask};
2408824088

24089+
static const Intrinsic::ID ScalableVlsegIntrIds[] = {
24090+
Intrinsic::riscv_vlseg2_mask, Intrinsic::riscv_vlseg3_mask,
24091+
Intrinsic::riscv_vlseg4_mask, Intrinsic::riscv_vlseg5_mask,
24092+
Intrinsic::riscv_vlseg6_mask, Intrinsic::riscv_vlseg7_mask,
24093+
Intrinsic::riscv_vlseg8_mask};
24094+
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/// Lower an interleaved load into a vlsegN intrinsic.
2409024096
///
2409124097
/// E.g. Lower an interleaved load (Factor = 2):
@@ -24155,6 +24161,12 @@ static const Intrinsic::ID FixedVssegIntrIds[] = {
2415524161
Intrinsic::riscv_seg6_store_mask, Intrinsic::riscv_seg7_store_mask,
2415624162
Intrinsic::riscv_seg8_store_mask};
2415724163

24164+
static const Intrinsic::ID ScalableVssegIntrIds[] = {
24165+
Intrinsic::riscv_vsseg2_mask, Intrinsic::riscv_vsseg3_mask,
24166+
Intrinsic::riscv_vsseg4_mask, Intrinsic::riscv_vsseg5_mask,
24167+
Intrinsic::riscv_vsseg6_mask, Intrinsic::riscv_vsseg7_mask,
24168+
Intrinsic::riscv_vsseg8_mask};
24169+
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/// Lower an interleaved store into a vssegN intrinsic.
2415924171
///
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/// E.g. Lower an interleaved store (Factor = 3):
@@ -24465,13 +24477,6 @@ bool RISCVTargetLowering::lowerInterleavedVPLoad(
2446524477
{FVTy, PtrTy, XLenTy},
2446624478
{Load->getArgOperand(0), Mask, EVL});
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} else {
24468-
static const Intrinsic::ID IntrMaskIds[] = {
24469-
Intrinsic::riscv_vlseg2_mask, Intrinsic::riscv_vlseg3_mask,
24470-
Intrinsic::riscv_vlseg4_mask, Intrinsic::riscv_vlseg5_mask,
24471-
Intrinsic::riscv_vlseg6_mask, Intrinsic::riscv_vlseg7_mask,
24472-
Intrinsic::riscv_vlseg8_mask,
24473-
};
24474-
2447524480
unsigned SEW = DL.getTypeSizeInBits(VTy->getElementType());
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unsigned NumElts = VTy->getElementCount().getKnownMinValue();
2447724482
Type *VecTupTy = TargetExtType::get(
@@ -24483,7 +24488,7 @@ bool RISCVTargetLowering::lowerInterleavedVPLoad(
2448324488
Value *PoisonVal = PoisonValue::get(VecTupTy);
2448424489

2448524490
Function *VlsegNFunc = Intrinsic::getOrInsertDeclaration(
24486-
Load->getModule(), IntrMaskIds[Factor - 2],
24491+
Load->getModule(), ScalableVlsegIntrIds[Factor - 2],
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{VecTupTy, PtrTy, Mask->getType(), EVL->getType()});
2448824493

2448924494
Value *Operands[] = {
@@ -24583,13 +24588,6 @@ bool RISCVTargetLowering::lowerInterleavedVPStore(
2458324588
return true;
2458424589
}
2458524590

24586-
static const Intrinsic::ID IntrMaskIds[] = {
24587-
Intrinsic::riscv_vsseg2_mask, Intrinsic::riscv_vsseg3_mask,
24588-
Intrinsic::riscv_vsseg4_mask, Intrinsic::riscv_vsseg5_mask,
24589-
Intrinsic::riscv_vsseg6_mask, Intrinsic::riscv_vsseg7_mask,
24590-
Intrinsic::riscv_vsseg8_mask,
24591-
};
24592-
2459324591
unsigned SEW = DL.getTypeSizeInBits(VTy->getElementType());
2459424592
unsigned NumElts = VTy->getElementCount().getKnownMinValue();
2459524593
Type *VecTupTy = TargetExtType::get(
@@ -24606,7 +24604,7 @@ bool RISCVTargetLowering::lowerInterleavedVPStore(
2460624604
VecInsertFunc, {StoredVal, InterleaveOperands[i], Builder.getInt32(i)});
2460724605

2460824606
Function *VssegNFunc = Intrinsic::getOrInsertDeclaration(
24609-
Store->getModule(), IntrMaskIds[Factor - 2],
24607+
Store->getModule(), ScalableVssegIntrIds[Factor - 2],
2461024608
{VecTupTy, PtrTy, Mask->getType(), EVL->getType()});
2461124609

2461224610
Value *Operands[] = {StoredVal, Store->getArgOperand(1), Mask, EVL,

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