@@ -18,13 +18,11 @@ define <8 x i16> @abdu_const(<8 x i16> %src1) {
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; CHECK-LABEL: abdu_const:
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; CHECK: // %bb.0:
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; CHECK-NEXT: movi v1.4s, #1
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- ; CHECK-NEXT: ushll2 v2.4s, v0.8h, #0
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- ; CHECK-NEXT: ushll v0.4s, v0.4h, #0
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- ; CHECK-NEXT: sub v0.4s, v0.4s, v1.4s
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- ; CHECK-NEXT: sub v1.4s, v2.4s, v1.4s
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- ; CHECK-NEXT: abs v1.4s, v1.4s
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- ; CHECK-NEXT: abs v0.4s, v0.4s
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- ; CHECK-NEXT: uzp1 v0.8h, v0.8h, v1.8h
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+ ; CHECK-NEXT: ushll v2.4s, v0.4h, #0
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+ ; CHECK-NEXT: ushll2 v0.4s, v0.8h, #0
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+ ; CHECK-NEXT: uabd v0.4s, v0.4s, v1.4s
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+ ; CHECK-NEXT: uabd v1.4s, v2.4s, v1.4s
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+ ; CHECK-NEXT: uzp1 v0.8h, v1.8h, v0.8h
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; CHECK-NEXT: ret
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%zextsrc1 = zext <8 x i16 > %src1 to <8 x i32 >
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%sub = sub <8 x i32 > %zextsrc1 , <i32 1 , i32 1 , i32 1 , i32 1 , i32 1 , i32 1 , i32 1 , i32 1 >
@@ -37,10 +35,10 @@ define <8 x i16> @abdu_const_lhs(<8 x i16> %src1) {
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; CHECK-LABEL: abdu_const_lhs:
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; CHECK: // %bb.0:
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; CHECK-NEXT: movi v1.4s, #1
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- ; CHECK-NEXT: usubw v2.4s, v1.4s, v0.4h
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- ; CHECK-NEXT: usubw2 v0.4s, v1.4s, v0.8h
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- ; CHECK-NEXT: abs v0.4s, v0.4s
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- ; CHECK-NEXT: abs v1.4s, v2.4s
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+ ; CHECK-NEXT: ushll v2.4s, v0.4h, #0
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+ ; CHECK-NEXT: ushll2 v0.4s, v0.8h, #0
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+ ; CHECK-NEXT: uabd v0.4s, v0.4s, v1 .4s
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+ ; CHECK-NEXT: uabd v1.4s, v2.4s, v1 .4s
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; CHECK-NEXT: uzp1 v0.8h, v1.8h, v0.8h
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; CHECK-NEXT: ret
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%zextsrc1 = zext <8 x i16 > %src1 to <8 x i32 >
@@ -53,13 +51,6 @@ define <8 x i16> @abdu_const_lhs(<8 x i16> %src1) {
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define <8 x i16 > @abdu_const_zero (<8 x i16 > %src1 ) {
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; CHECK-LABEL: abdu_const_zero:
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; CHECK: // %bb.0:
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- ; CHECK-NEXT: movi v1.2d, #0000000000000000
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- ; CHECK-NEXT: ushll v2.4s, v0.4h, #0
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- ; CHECK-NEXT: usubw2 v0.4s, v1.4s, v0.8h
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- ; CHECK-NEXT: neg v1.4s, v2.4s
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- ; CHECK-NEXT: abs v0.4s, v0.4s
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- ; CHECK-NEXT: abs v1.4s, v1.4s
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- ; CHECK-NEXT: uzp1 v0.8h, v1.8h, v0.8h
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; CHECK-NEXT: ret
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%zextsrc1 = zext <8 x i16 > %src1 to <8 x i32 >
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%sub = sub <8 x i32 > <i32 0 , i32 0 , i32 0 , i32 0 , i32 0 , i32 0 , i32 0 , i32 0 >, %zextsrc1
@@ -328,13 +319,11 @@ define <8 x i16> @abds_const(<8 x i16> %src1) {
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; CHECK-LABEL: abds_const:
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; CHECK: // %bb.0:
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; CHECK-NEXT: movi v1.4s, #1
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- ; CHECK-NEXT: sshll2 v2.4s, v0.8h, #0
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- ; CHECK-NEXT: sshll v0.4s, v0.4h, #0
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- ; CHECK-NEXT: sub v0.4s, v0.4s, v1.4s
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- ; CHECK-NEXT: sub v1.4s, v2.4s, v1.4s
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- ; CHECK-NEXT: abs v1.4s, v1.4s
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- ; CHECK-NEXT: abs v0.4s, v0.4s
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- ; CHECK-NEXT: uzp1 v0.8h, v0.8h, v1.8h
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+ ; CHECK-NEXT: sshll v2.4s, v0.4h, #0
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+ ; CHECK-NEXT: sshll2 v0.4s, v0.8h, #0
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+ ; CHECK-NEXT: sabd v0.4s, v0.4s, v1.4s
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+ ; CHECK-NEXT: sabd v1.4s, v2.4s, v1.4s
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+ ; CHECK-NEXT: uzp1 v0.8h, v1.8h, v0.8h
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; CHECK-NEXT: ret
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%zextsrc1 = sext <8 x i16 > %src1 to <8 x i32 >
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%sub = sub <8 x i32 > %zextsrc1 , <i32 1 , i32 1 , i32 1 , i32 1 , i32 1 , i32 1 , i32 1 , i32 1 >
@@ -347,10 +336,10 @@ define <8 x i16> @abds_const_lhs(<8 x i16> %src1) {
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; CHECK-LABEL: abds_const_lhs:
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; CHECK: // %bb.0:
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; CHECK-NEXT: movi v1.4s, #1
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- ; CHECK-NEXT: ssubw v2.4s, v1.4s, v0.4h
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- ; CHECK-NEXT: ssubw2 v0.4s, v1.4s, v0.8h
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- ; CHECK-NEXT: abs v0.4s, v0.4s
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- ; CHECK-NEXT: abs v1.4s, v2.4s
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+ ; CHECK-NEXT: sshll v2.4s, v0.4h, #0
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+ ; CHECK-NEXT: sshll2 v0.4s, v0.8h, #0
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+ ; CHECK-NEXT: sabd v0.4s, v0.4s, v1 .4s
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+ ; CHECK-NEXT: sabd v1.4s, v2.4s, v1 .4s
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; CHECK-NEXT: uzp1 v0.8h, v1.8h, v0.8h
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; CHECK-NEXT: ret
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%zextsrc1 = sext <8 x i16 > %src1 to <8 x i32 >
@@ -363,10 +352,8 @@ define <8 x i16> @abds_const_lhs(<8 x i16> %src1) {
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define <8 x i16 > @abds_const_zero (<8 x i16 > %src1 ) {
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; CHECK-LABEL: abds_const_zero:
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; CHECK: // %bb.0:
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- ; CHECK-NEXT: movi v1.2d, #0000000000000000
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- ; CHECK-NEXT: sshll v2.4s, v0.4h, #0
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- ; CHECK-NEXT: ssubw2 v0.4s, v1.4s, v0.8h
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- ; CHECK-NEXT: neg v1.4s, v2.4s
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+ ; CHECK-NEXT: sshll v1.4s, v0.4h, #0
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+ ; CHECK-NEXT: sshll2 v0.4s, v0.8h, #0
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; CHECK-NEXT: abs v0.4s, v0.4s
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; CHECK-NEXT: abs v1.4s, v1.4s
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; CHECK-NEXT: uzp1 v0.8h, v1.8h, v0.8h
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