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[ARM] Port shouldBeAdjustedToZero to ARM
1 parent 320f682 commit b9fcf26

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8 files changed

+712
-305
lines changed

8 files changed

+712
-305
lines changed

‎llvm/lib/Target/ARM/ARMISelLowering.cpp

Lines changed: 33 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -4839,14 +4839,45 @@ static bool isFloatingPointZero(SDValue Op) {
48394839
return false;
48404840
}
48414841

4842+
static bool shouldBeAdjustedToZero(SDValue LHS, APInt C, ISD::CondCode &CC) {
4843+
// setlt and setge are changed to MI and PL for zero respectively, so it is
4844+
// safe.
4845+
if (C.isAllOnes() && (CC == ISD::SETLE || CC == ISD::SETGT)) {
4846+
CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE;
4847+
return true;
4848+
}
4849+
4850+
// On ARM, adds and subs set the V flags correctly, which means the optimizer
4851+
// can condense to a single adds/subs
4852+
switch (LHS.getOpcode()) {
4853+
case ISD::ADD:
4854+
case ISD::SUB:
4855+
break;
4856+
default:
4857+
return false;
4858+
}
4859+
4860+
if (C.isOne() && (CC == ISD::SETLT || CC == ISD::SETGE)) {
4861+
CC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGT;
4862+
return true;
4863+
}
4864+
4865+
return false;
4866+
}
4867+
48424868
/// Returns appropriate ARM CMP (cmp) and corresponding condition code for
48434869
/// the given operands.
48444870
SDValue ARMTargetLowering::getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
48454871
SDValue &ARMcc, SelectionDAG &DAG,
48464872
const SDLoc &dl) const {
48474873
if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS.getNode())) {
4848-
unsigned C = RHSC->getZExtValue();
4849-
if (!isLegalICmpImmediate((int32_t)C)) {
4874+
APInt CInt = RHSC->getAPIntValue();
4875+
unsigned C = CInt.getZExtValue();
4876+
if (shouldBeAdjustedToZero(LHS, CInt, CC)) {
4877+
// Adjust the constant to zero.
4878+
// CC has already been adjusted.
4879+
RHS = DAG.getConstant(0, dl, MVT::i32);
4880+
} else if (!isLegalICmpImmediate((int32_t)C)) {
48504881
// Constant does not fit, try adjusting it by one.
48514882
switch (CC) {
48524883
default: break;

‎llvm/test/CodeGen/ARM/arm-shrink-wrapping-linux.ll

Lines changed: 16 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -19,10 +19,9 @@ define fastcc ptr @wrongUseOfPostDominate(ptr readonly %s, i32 %off, ptr readnon
1919
; ENABLE: @ %bb.0: @ %entry
2020
; ENABLE-NEXT: .save {r11, lr}
2121
; ENABLE-NEXT: push {r11, lr}
22-
; ENABLE-NEXT: cmn r1, #1
23-
; ENABLE-NEXT: ble .LBB0_7
24-
; ENABLE-NEXT: @ %bb.1: @ %while.cond.preheader
2522
; ENABLE-NEXT: cmp r1, #0
23+
; ENABLE-NEXT: bmi .LBB0_7
24+
; ENABLE-NEXT: @ %bb.1: @ %while.cond.preheader
2625
; ENABLE-NEXT: beq .LBB0_6
2726
; ENABLE-NEXT: @ %bb.2: @ %while.cond.preheader
2827
; ENABLE-NEXT: cmp r0, r2
@@ -66,16 +65,16 @@ define fastcc ptr @wrongUseOfPostDominate(ptr readonly %s, i32 %off, ptr readnon
6665
; ENABLE-NEXT: mov r0, r3
6766
; ENABLE-NEXT: ldrb r12, [r0, #-1]!
6867
; ENABLE-NEXT: sxtb lr, r12
69-
; ENABLE-NEXT: cmn lr, #1
70-
; ENABLE-NEXT: bgt .LBB0_7
68+
; ENABLE-NEXT: cmp lr, #0
69+
; ENABLE-NEXT: bpl .LBB0_7
7170
; ENABLE-NEXT: @ %bb.11: @ %if.then7
7271
; ENABLE-NEXT: @ in Loop: Header=BB0_7 Depth=1
7372
; ENABLE-NEXT: cmp r0, r2
7473
; ENABLE-NEXT: bls .LBB0_7
7574
; ENABLE-NEXT: @ %bb.12: @ %land.rhs14.preheader
7675
; ENABLE-NEXT: @ in Loop: Header=BB0_7 Depth=1
77-
; ENABLE-NEXT: cmn lr, #1
78-
; ENABLE-NEXT: bgt .LBB0_7
76+
; ENABLE-NEXT: cmp lr, #0
77+
; ENABLE-NEXT: bpl .LBB0_7
7978
; ENABLE-NEXT: @ %bb.13: @ %land.rhs14.preheader
8079
; ENABLE-NEXT: @ in Loop: Header=BB0_7 Depth=1
8180
; ENABLE-NEXT: cmp r12, #191
@@ -93,9 +92,9 @@ define fastcc ptr @wrongUseOfPostDominate(ptr readonly %s, i32 %off, ptr readnon
9392
; ENABLE-NEXT: @ in Loop: Header=BB0_15 Depth=2
9493
; ENABLE-NEXT: mov r3, r0
9594
; ENABLE-NEXT: ldrsb lr, [r3], #-1
96-
; ENABLE-NEXT: cmn lr, #1
95+
; ENABLE-NEXT: cmp lr, #0
9796
; ENABLE-NEXT: uxtb r12, lr
98-
; ENABLE-NEXT: bgt .LBB0_7
97+
; ENABLE-NEXT: bpl .LBB0_7
9998
; ENABLE-NEXT: @ %bb.17: @ %while.body24.land.rhs14_crit_edge
10099
; ENABLE-NEXT: @ in Loop: Header=BB0_15 Depth=2
101100
; ENABLE-NEXT: cmp r12, #192
@@ -109,10 +108,9 @@ define fastcc ptr @wrongUseOfPostDominate(ptr readonly %s, i32 %off, ptr readnon
109108
; DISABLE: @ %bb.0: @ %entry
110109
; DISABLE-NEXT: .save {r11, lr}
111110
; DISABLE-NEXT: push {r11, lr}
112-
; DISABLE-NEXT: cmn r1, #1
113-
; DISABLE-NEXT: ble .LBB0_7
114-
; DISABLE-NEXT: @ %bb.1: @ %while.cond.preheader
115111
; DISABLE-NEXT: cmp r1, #0
112+
; DISABLE-NEXT: bmi .LBB0_7
113+
; DISABLE-NEXT: @ %bb.1: @ %while.cond.preheader
116114
; DISABLE-NEXT: beq .LBB0_6
117115
; DISABLE-NEXT: @ %bb.2: @ %while.cond.preheader
118116
; DISABLE-NEXT: cmp r0, r2
@@ -156,16 +154,16 @@ define fastcc ptr @wrongUseOfPostDominate(ptr readonly %s, i32 %off, ptr readnon
156154
; DISABLE-NEXT: mov r0, r3
157155
; DISABLE-NEXT: ldrb r12, [r0, #-1]!
158156
; DISABLE-NEXT: sxtb lr, r12
159-
; DISABLE-NEXT: cmn lr, #1
160-
; DISABLE-NEXT: bgt .LBB0_7
157+
; DISABLE-NEXT: cmp lr, #0
158+
; DISABLE-NEXT: bpl .LBB0_7
161159
; DISABLE-NEXT: @ %bb.11: @ %if.then7
162160
; DISABLE-NEXT: @ in Loop: Header=BB0_7 Depth=1
163161
; DISABLE-NEXT: cmp r0, r2
164162
; DISABLE-NEXT: bls .LBB0_7
165163
; DISABLE-NEXT: @ %bb.12: @ %land.rhs14.preheader
166164
; DISABLE-NEXT: @ in Loop: Header=BB0_7 Depth=1
167-
; DISABLE-NEXT: cmn lr, #1
168-
; DISABLE-NEXT: bgt .LBB0_7
165+
; DISABLE-NEXT: cmp lr, #0
166+
; DISABLE-NEXT: bpl .LBB0_7
169167
; DISABLE-NEXT: @ %bb.13: @ %land.rhs14.preheader
170168
; DISABLE-NEXT: @ in Loop: Header=BB0_7 Depth=1
171169
; DISABLE-NEXT: cmp r12, #191
@@ -183,9 +181,9 @@ define fastcc ptr @wrongUseOfPostDominate(ptr readonly %s, i32 %off, ptr readnon
183181
; DISABLE-NEXT: @ in Loop: Header=BB0_15 Depth=2
184182
; DISABLE-NEXT: mov r3, r0
185183
; DISABLE-NEXT: ldrsb lr, [r3], #-1
186-
; DISABLE-NEXT: cmn lr, #1
184+
; DISABLE-NEXT: cmp lr, #0
187185
; DISABLE-NEXT: uxtb r12, lr
188-
; DISABLE-NEXT: bgt .LBB0_7
186+
; DISABLE-NEXT: bpl .LBB0_7
189187
; DISABLE-NEXT: @ %bb.17: @ %while.body24.land.rhs14_crit_edge
190188
; DISABLE-NEXT: @ in Loop: Header=BB0_15 Depth=2
191189
; DISABLE-NEXT: cmp r12, #192

‎llvm/test/CodeGen/ARM/consthoist-icmpimm.ll

Lines changed: 72 additions & 72 deletions
Original file line numberDiff line numberDiff line change
@@ -44,19 +44,19 @@ define i32 @icmp64_sge_0(i64 %x, i64 %y, i32 %a, i32 %b, i1 %c) {
4444
; CHECKV7M-NEXT: ldrd r2, r0, [sp]
4545
; CHECKV7M-NEXT: beq .LBB0_2
4646
; CHECKV7M-NEXT: @ %bb.1: @ %then
47-
; CHECKV7M-NEXT: cmp.w r3, #-1
47+
; CHECKV7M-NEXT: cmp r3, #0
4848
; CHECKV7M-NEXT: mov r3, r0
49-
; CHECKV7M-NEXT: it gt
50-
; CHECKV7M-NEXT: movgt r3, r2
51-
; CHECKV7M-NEXT: cmp.w r1, #-1
52-
; CHECKV7M-NEXT: it gt
53-
; CHECKV7M-NEXT: movgt r0, r2
49+
; CHECKV7M-NEXT: it ge
50+
; CHECKV7M-NEXT: movge r3, r2
51+
; CHECKV7M-NEXT: cmp r1, #0
52+
; CHECKV7M-NEXT: it ge
53+
; CHECKV7M-NEXT: movge r0, r2
5454
; CHECKV7M-NEXT: add r0, r3
5555
; CHECKV7M-NEXT: bx lr
5656
; CHECKV7M-NEXT: .LBB0_2: @ %else
57-
; CHECKV7M-NEXT: cmp.w r1, #-1
58-
; CHECKV7M-NEXT: it gt
59-
; CHECKV7M-NEXT: movgt r0, r2
57+
; CHECKV7M-NEXT: cmp r1, #0
58+
; CHECKV7M-NEXT: it ge
59+
; CHECKV7M-NEXT: movge r0, r2
6060
; CHECKV7M-NEXT: bx lr
6161
;
6262
; CHECKV7A-LABEL: icmp64_sge_0:
@@ -66,19 +66,19 @@ define i32 @icmp64_sge_0(i64 %x, i64 %y, i32 %a, i32 %b, i1 %c) {
6666
; CHECKV7A-NEXT: lsls r2, r2, #31
6767
; CHECKV7A-NEXT: beq .LBB0_2
6868
; CHECKV7A-NEXT: @ %bb.1: @ %then
69-
; CHECKV7A-NEXT: cmp.w r3, #-1
69+
; CHECKV7A-NEXT: cmp r3, #0
7070
; CHECKV7A-NEXT: mov r2, r0
71-
; CHECKV7A-NEXT: it gt
72-
; CHECKV7A-NEXT: movgt r2, r12
73-
; CHECKV7A-NEXT: cmp.w r1, #-1
74-
; CHECKV7A-NEXT: it gt
75-
; CHECKV7A-NEXT: movgt r0, r12
71+
; CHECKV7A-NEXT: it ge
72+
; CHECKV7A-NEXT: movge r2, r12
73+
; CHECKV7A-NEXT: cmp r1, #0
74+
; CHECKV7A-NEXT: it ge
75+
; CHECKV7A-NEXT: movge r0, r12
7676
; CHECKV7A-NEXT: add r0, r2
7777
; CHECKV7A-NEXT: bx lr
7878
; CHECKV7A-NEXT: .LBB0_2: @ %else
79-
; CHECKV7A-NEXT: cmp.w r1, #-1
80-
; CHECKV7A-NEXT: it gt
81-
; CHECKV7A-NEXT: movgt r0, r12
79+
; CHECKV7A-NEXT: cmp r1, #0
80+
; CHECKV7A-NEXT: it ge
81+
; CHECKV7A-NEXT: movge r0, r12
8282
; CHECKV7A-NEXT: bx lr
8383
br i1 %c, label %then, label %else
8484
then:
@@ -135,19 +135,19 @@ define i32 @icmp64_sgt_m1(i64 %x, i64 %y, i32 %a, i32 %b, i1 %c) {
135135
; CHECKV7M-NEXT: ldrd r2, r0, [sp]
136136
; CHECKV7M-NEXT: beq .LBB1_2
137137
; CHECKV7M-NEXT: @ %bb.1: @ %then
138-
; CHECKV7M-NEXT: cmp.w r3, #-1
138+
; CHECKV7M-NEXT: cmp r3, #0
139139
; CHECKV7M-NEXT: mov r3, r0
140-
; CHECKV7M-NEXT: it gt
141-
; CHECKV7M-NEXT: movgt r3, r2
142-
; CHECKV7M-NEXT: cmp.w r1, #-1
143-
; CHECKV7M-NEXT: it gt
144-
; CHECKV7M-NEXT: movgt r0, r2
140+
; CHECKV7M-NEXT: it ge
141+
; CHECKV7M-NEXT: movge r3, r2
142+
; CHECKV7M-NEXT: cmp r1, #0
143+
; CHECKV7M-NEXT: it ge
144+
; CHECKV7M-NEXT: movge r0, r2
145145
; CHECKV7M-NEXT: add r0, r3
146146
; CHECKV7M-NEXT: bx lr
147147
; CHECKV7M-NEXT: .LBB1_2: @ %else
148-
; CHECKV7M-NEXT: cmp.w r3, #-1
149-
; CHECKV7M-NEXT: it gt
150-
; CHECKV7M-NEXT: movgt r0, r2
148+
; CHECKV7M-NEXT: cmp r3, #0
149+
; CHECKV7M-NEXT: it ge
150+
; CHECKV7M-NEXT: movge r0, r2
151151
; CHECKV7M-NEXT: bx lr
152152
;
153153
; CHECKV7A-LABEL: icmp64_sgt_m1:
@@ -157,19 +157,19 @@ define i32 @icmp64_sgt_m1(i64 %x, i64 %y, i32 %a, i32 %b, i1 %c) {
157157
; CHECKV7A-NEXT: lsls r2, r2, #31
158158
; CHECKV7A-NEXT: beq .LBB1_2
159159
; CHECKV7A-NEXT: @ %bb.1: @ %then
160-
; CHECKV7A-NEXT: cmp.w r3, #-1
160+
; CHECKV7A-NEXT: cmp r3, #0
161161
; CHECKV7A-NEXT: mov r2, r0
162-
; CHECKV7A-NEXT: it gt
163-
; CHECKV7A-NEXT: movgt r2, r12
164-
; CHECKV7A-NEXT: cmp.w r1, #-1
165-
; CHECKV7A-NEXT: it gt
166-
; CHECKV7A-NEXT: movgt r0, r12
162+
; CHECKV7A-NEXT: it ge
163+
; CHECKV7A-NEXT: movge r2, r12
164+
; CHECKV7A-NEXT: cmp r1, #0
165+
; CHECKV7A-NEXT: it ge
166+
; CHECKV7A-NEXT: movge r0, r12
167167
; CHECKV7A-NEXT: add r0, r2
168168
; CHECKV7A-NEXT: bx lr
169169
; CHECKV7A-NEXT: .LBB1_2: @ %else
170-
; CHECKV7A-NEXT: cmp.w r3, #-1
171-
; CHECKV7A-NEXT: it gt
172-
; CHECKV7A-NEXT: movgt r0, r12
170+
; CHECKV7A-NEXT: cmp r3, #0
171+
; CHECKV7A-NEXT: it ge
172+
; CHECKV7A-NEXT: movge r0, r12
173173
; CHECKV7A-NEXT: bx lr
174174
br i1 %c, label %then, label %else
175175
then:
@@ -227,19 +227,19 @@ define i32 @icmp32_sge_0(i32 %x, i32 %y, i32 %a, i32 %b, i1 %c) {
227227
; CHECKV7M-NEXT: lsls r3, r3, #31
228228
; CHECKV7M-NEXT: beq .LBB2_2
229229
; CHECKV7M-NEXT: @ %bb.1: @ %then
230-
; CHECKV7M-NEXT: cmp.w r1, #-1
230+
; CHECKV7M-NEXT: cmp r1, #0
231231
; CHECKV7M-NEXT: mov r1, r12
232-
; CHECKV7M-NEXT: it gt
233-
; CHECKV7M-NEXT: movgt r1, r2
234-
; CHECKV7M-NEXT: cmp.w r0, #-1
235-
; CHECKV7M-NEXT: it gt
236-
; CHECKV7M-NEXT: movgt r12, r2
232+
; CHECKV7M-NEXT: it ge
233+
; CHECKV7M-NEXT: movge r1, r2
234+
; CHECKV7M-NEXT: cmp r0, #0
235+
; CHECKV7M-NEXT: it ge
236+
; CHECKV7M-NEXT: movge r12, r2
237237
; CHECKV7M-NEXT: add.w r0, r12, r1
238238
; CHECKV7M-NEXT: bx lr
239239
; CHECKV7M-NEXT: .LBB2_2: @ %else
240-
; CHECKV7M-NEXT: cmp.w r0, #-1
241-
; CHECKV7M-NEXT: it gt
242-
; CHECKV7M-NEXT: movgt r12, r2
240+
; CHECKV7M-NEXT: cmp r0, #0
241+
; CHECKV7M-NEXT: it ge
242+
; CHECKV7M-NEXT: movge r12, r2
243243
; CHECKV7M-NEXT: mov r0, r12
244244
; CHECKV7M-NEXT: bx lr
245245
;
@@ -250,19 +250,19 @@ define i32 @icmp32_sge_0(i32 %x, i32 %y, i32 %a, i32 %b, i1 %c) {
250250
; CHECKV7A-NEXT: lsls r3, r3, #31
251251
; CHECKV7A-NEXT: beq .LBB2_2
252252
; CHECKV7A-NEXT: @ %bb.1: @ %then
253-
; CHECKV7A-NEXT: cmp.w r1, #-1
253+
; CHECKV7A-NEXT: cmp r1, #0
254254
; CHECKV7A-NEXT: mov r1, r12
255-
; CHECKV7A-NEXT: it gt
256-
; CHECKV7A-NEXT: movgt r1, r2
257-
; CHECKV7A-NEXT: cmp.w r0, #-1
258-
; CHECKV7A-NEXT: it gt
259-
; CHECKV7A-NEXT: movgt r12, r2
255+
; CHECKV7A-NEXT: it ge
256+
; CHECKV7A-NEXT: movge r1, r2
257+
; CHECKV7A-NEXT: cmp r0, #0
258+
; CHECKV7A-NEXT: it ge
259+
; CHECKV7A-NEXT: movge r12, r2
260260
; CHECKV7A-NEXT: add.w r0, r12, r1
261261
; CHECKV7A-NEXT: bx lr
262262
; CHECKV7A-NEXT: .LBB2_2: @ %else
263-
; CHECKV7A-NEXT: cmp.w r0, #-1
264-
; CHECKV7A-NEXT: it gt
265-
; CHECKV7A-NEXT: movgt r12, r2
263+
; CHECKV7A-NEXT: cmp r0, #0
264+
; CHECKV7A-NEXT: it ge
265+
; CHECKV7A-NEXT: movge r12, r2
266266
; CHECKV7A-NEXT: mov r0, r12
267267
; CHECKV7A-NEXT: bx lr
268268
br i1 %c, label %then, label %else
@@ -321,19 +321,19 @@ define i32 @icmp32_sgt_m1(i32 %x, i32 %y, i32 %a, i32 %b, i1 %c) {
321321
; CHECKV7M-NEXT: lsls r3, r3, #31
322322
; CHECKV7M-NEXT: beq .LBB3_2
323323
; CHECKV7M-NEXT: @ %bb.1: @ %then
324-
; CHECKV7M-NEXT: cmp.w r1, #-1
324+
; CHECKV7M-NEXT: cmp r1, #0
325325
; CHECKV7M-NEXT: mov r1, r12
326-
; CHECKV7M-NEXT: it gt
327-
; CHECKV7M-NEXT: movgt r1, r2
328-
; CHECKV7M-NEXT: cmp.w r0, #-1
329-
; CHECKV7M-NEXT: it gt
330-
; CHECKV7M-NEXT: movgt r12, r2
326+
; CHECKV7M-NEXT: it ge
327+
; CHECKV7M-NEXT: movge r1, r2
328+
; CHECKV7M-NEXT: cmp r0, #0
329+
; CHECKV7M-NEXT: it ge
330+
; CHECKV7M-NEXT: movge r12, r2
331331
; CHECKV7M-NEXT: add.w r0, r12, r1
332332
; CHECKV7M-NEXT: bx lr
333333
; CHECKV7M-NEXT: .LBB3_2: @ %else
334-
; CHECKV7M-NEXT: cmp.w r1, #-1
335-
; CHECKV7M-NEXT: it gt
336-
; CHECKV7M-NEXT: movgt r12, r2
334+
; CHECKV7M-NEXT: cmp r1, #0
335+
; CHECKV7M-NEXT: it ge
336+
; CHECKV7M-NEXT: movge r12, r2
337337
; CHECKV7M-NEXT: mov r0, r12
338338
; CHECKV7M-NEXT: bx lr
339339
;
@@ -344,19 +344,19 @@ define i32 @icmp32_sgt_m1(i32 %x, i32 %y, i32 %a, i32 %b, i1 %c) {
344344
; CHECKV7A-NEXT: lsls r3, r3, #31
345345
; CHECKV7A-NEXT: beq .LBB3_2
346346
; CHECKV7A-NEXT: @ %bb.1: @ %then
347-
; CHECKV7A-NEXT: cmp.w r1, #-1
347+
; CHECKV7A-NEXT: cmp r1, #0
348348
; CHECKV7A-NEXT: mov r1, r12
349-
; CHECKV7A-NEXT: it gt
350-
; CHECKV7A-NEXT: movgt r1, r2
351-
; CHECKV7A-NEXT: cmp.w r0, #-1
352-
; CHECKV7A-NEXT: it gt
353-
; CHECKV7A-NEXT: movgt r12, r2
349+
; CHECKV7A-NEXT: it ge
350+
; CHECKV7A-NEXT: movge r1, r2
351+
; CHECKV7A-NEXT: cmp r0, #0
352+
; CHECKV7A-NEXT: it ge
353+
; CHECKV7A-NEXT: movge r12, r2
354354
; CHECKV7A-NEXT: add.w r0, r12, r1
355355
; CHECKV7A-NEXT: bx lr
356356
; CHECKV7A-NEXT: .LBB3_2: @ %else
357-
; CHECKV7A-NEXT: cmp.w r1, #-1
358-
; CHECKV7A-NEXT: it gt
359-
; CHECKV7A-NEXT: movgt r12, r2
357+
; CHECKV7A-NEXT: cmp r1, #0
358+
; CHECKV7A-NEXT: it ge
359+
; CHECKV7A-NEXT: movge r12, r2
360360
; CHECKV7A-NEXT: mov r0, r12
361361
; CHECKV7A-NEXT: bx lr
362362
br i1 %c, label %then, label %else

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