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[RISCV][GISel] Remove -disable-gisel-legality-check from scalar tests. NFC
Adjust a couple tests so they can pass the check.
1 parent d492001 commit b904166

20 files changed

+59
-69
lines changed

‎llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/alu-rv32.mir

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
22
# RUN: llc -mtriple=riscv32 -mattr=+m -run-pass=regbankselect \
3-
# RUN: -disable-gisel-legality-check -simplify-mir -verify-machineinstrs %s \
3+
# RUN: -simplify-mir -verify-machineinstrs %s \
44
# RUN: -o - | FileCheck -check-prefix=RV32I %s
55

66
---

‎llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/alu-rv64.mir

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
22
# RUN: llc -mtriple=riscv64 -mattr=+m -run-pass=regbankselect \
3-
# RUN: -disable-gisel-legality-check -simplify-mir -verify-machineinstrs %s \
3+
# RUN: -simplify-mir -verify-machineinstrs %s \
44
# RUN: -o - | FileCheck -check-prefix=RV64I %s
55

66
---

‎llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/copy-rv32.mir

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
22
# RUN: llc -mtriple=riscv32 -run-pass=regbankselect \
3-
# RUN: -disable-gisel-legality-check -simplify-mir -verify-machineinstrs %s \
3+
# RUN: -simplify-mir -verify-machineinstrs %s \
44
# RUN: -o - | FileCheck -check-prefix=RV32I %s
55

66
---

‎llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/copy-rv64.mir

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
22
# RUN: llc -mtriple=riscv64 -run-pass=regbankselect \
3-
# RUN: -disable-gisel-legality-check -simplify-mir -verify-machineinstrs %s \
3+
# RUN: -simplify-mir -verify-machineinstrs %s \
44
# RUN: -o - | FileCheck -check-prefix=RV64I %s
55

66
---

‎llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/ext-trunc-rv64.mir

Lines changed: 13 additions & 31 deletions
Original file line numberDiff line numberDiff line change
@@ -1,32 +1,26 @@
11
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
22
# RUN: llc -mtriple=riscv64 -run-pass=regbankselect \
3-
# RUN: -disable-gisel-legality-check -simplify-mir -verify-machineinstrs %s \
3+
# RUN: -simplify-mir -verify-machineinstrs %s \
44
# RUN: -o - | FileCheck -check-prefix=RV64I %s
55

66
---
77
name: anyext_i32_i64
88
legalized: true
99
body: |
1010
bb.0.entry:
11-
liveins: $x10, $x11
11+
liveins: $x10
1212
1313
; RV64I-LABEL: name: anyext_i32_i64
14-
; RV64I: liveins: $x10, $x11
14+
; RV64I: liveins: $x10
1515
; RV64I-NEXT: {{ $}}
1616
; RV64I-NEXT: [[COPY:%[0-9]+]]:gprb(s64) = COPY $x10
1717
; RV64I-NEXT: [[TRUNC:%[0-9]+]]:gprb(s32) = G_TRUNC [[COPY]](s64)
18-
; RV64I-NEXT: [[COPY1:%[0-9]+]]:gprb(s64) = COPY $x11
19-
; RV64I-NEXT: [[TRUNC1:%[0-9]+]]:gprb(s32) = G_TRUNC [[COPY1]](s64)
20-
; RV64I-NEXT: [[ADD:%[0-9]+]]:gprb(s32) = G_ADD [[TRUNC]], [[TRUNC1]]
21-
; RV64I-NEXT: [[ANYEXT:%[0-9]+]]:gprb(s64) = G_ANYEXT [[ADD]](s32)
18+
; RV64I-NEXT: [[ANYEXT:%[0-9]+]]:gprb(s64) = G_ANYEXT [[TRUNC]](s32)
2219
; RV64I-NEXT: $x10 = COPY [[ANYEXT]](s64)
2320
; RV64I-NEXT: PseudoRET implicit $x10
2421
%2:_(s64) = COPY $x10
2522
%0:_(s32) = G_TRUNC %2(s64)
26-
%3:_(s64) = COPY $x11
27-
%1:_(s32) = G_TRUNC %3(s64)
28-
%4:_(s32) = G_ADD %0, %1
29-
%5:_(s64) = G_ANYEXT %4(s32)
23+
%5:_(s64) = G_ANYEXT %0(s32)
3024
$x10 = COPY %5(s64)
3125
PseudoRET implicit $x10
3226
@@ -36,25 +30,19 @@ name: sext_i32_i64
3630
legalized: true
3731
body: |
3832
bb.0.entry:
39-
liveins: $x10, $x11
33+
liveins: $x10
4034
4135
; RV64I-LABEL: name: sext_i32_i64
42-
; RV64I: liveins: $x10, $x11
36+
; RV64I: liveins: $x10
4337
; RV64I-NEXT: {{ $}}
4438
; RV64I-NEXT: [[COPY:%[0-9]+]]:gprb(s64) = COPY $x10
4539
; RV64I-NEXT: [[TRUNC:%[0-9]+]]:gprb(s32) = G_TRUNC [[COPY]](s64)
46-
; RV64I-NEXT: [[COPY1:%[0-9]+]]:gprb(s64) = COPY $x11
47-
; RV64I-NEXT: [[TRUNC1:%[0-9]+]]:gprb(s32) = G_TRUNC [[COPY1]](s64)
48-
; RV64I-NEXT: [[ADD:%[0-9]+]]:gprb(s32) = G_ADD [[TRUNC]], [[TRUNC1]]
49-
; RV64I-NEXT: [[SEXT:%[0-9]+]]:gprb(s64) = G_SEXT [[ADD]](s32)
40+
; RV64I-NEXT: [[SEXT:%[0-9]+]]:gprb(s64) = G_SEXT [[TRUNC]](s32)
5041
; RV64I-NEXT: $x10 = COPY [[SEXT]](s64)
5142
; RV64I-NEXT: PseudoRET implicit $x10
5243
%2:_(s64) = COPY $x10
5344
%0:_(s32) = G_TRUNC %2(s64)
54-
%3:_(s64) = COPY $x11
55-
%1:_(s32) = G_TRUNC %3(s64)
56-
%4:_(s32) = G_ADD %0, %1
57-
%5:_(s64) = G_SEXT %4(s32)
45+
%5:_(s64) = G_SEXT %0(s32)
5846
$x10 = COPY %5(s64)
5947
PseudoRET implicit $x10
6048
@@ -64,25 +52,19 @@ name: zext_i32_i64
6452
legalized: true
6553
body: |
6654
bb.0.entry:
67-
liveins: $x10, $x11
55+
liveins: $x10
6856
6957
; RV64I-LABEL: name: zext_i32_i64
70-
; RV64I: liveins: $x10, $x11
58+
; RV64I: liveins: $x10
7159
; RV64I-NEXT: {{ $}}
7260
; RV64I-NEXT: [[COPY:%[0-9]+]]:gprb(s64) = COPY $x10
7361
; RV64I-NEXT: [[TRUNC:%[0-9]+]]:gprb(s32) = G_TRUNC [[COPY]](s64)
74-
; RV64I-NEXT: [[COPY1:%[0-9]+]]:gprb(s64) = COPY $x11
75-
; RV64I-NEXT: [[TRUNC1:%[0-9]+]]:gprb(s32) = G_TRUNC [[COPY1]](s64)
76-
; RV64I-NEXT: [[ADD:%[0-9]+]]:gprb(s32) = G_ADD [[TRUNC]], [[TRUNC1]]
77-
; RV64I-NEXT: [[ZEXT:%[0-9]+]]:gprb(s64) = G_ZEXT [[ADD]](s32)
62+
; RV64I-NEXT: [[ZEXT:%[0-9]+]]:gprb(s64) = G_ZEXT [[TRUNC]](s32)
7863
; RV64I-NEXT: $x10 = COPY [[ZEXT]](s64)
7964
; RV64I-NEXT: PseudoRET implicit $x10
8065
%2:_(s64) = COPY $x10
8166
%0:_(s32) = G_TRUNC %2(s64)
82-
%3:_(s64) = COPY $x11
83-
%1:_(s32) = G_TRUNC %3(s64)
84-
%4:_(s32) = G_ADD %0, %1
85-
%5:_(s64) = G_ZEXT %4(s32)
67+
%5:_(s64) = G_ZEXT %0(s32)
8668
$x10 = COPY %5(s64)
8769
PseudoRET implicit $x10
8870

‎llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fp-select-rv32.mir

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
22
# RUN: llc -mtriple=riscv32 -mattr=+d -run-pass=regbankselect \
3-
# RUN: -disable-gisel-legality-check -simplify-mir -verify-machineinstrs %s \
3+
# RUN: -simplify-mir -verify-machineinstrs %s \
44
# RUN: -o - | FileCheck -check-prefix=RV32I %s
55

66
---

‎llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fp-select-rv64.mir

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
22
# RUN: llc -mtriple=riscv64 -mattr=+d -run-pass=regbankselect \
3-
# RUN: -disable-gisel-legality-check -simplify-mir -verify-machineinstrs %s \
3+
# RUN: -simplify-mir -verify-machineinstrs %s \
44
# RUN: -o - | FileCheck -check-prefix=RV32I %s
55

66
---

‎llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/global-rv32.mir

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
22
# RUN: llc -mtriple=riscv32 -run-pass=regbankselect \
3-
# RUN: -disable-gisel-legality-check -simplify-mir -verify-machineinstrs %s \
3+
# RUN: -simplify-mir -verify-machineinstrs %s \
44
# RUN: -o - | FileCheck -check-prefix=RV32I %s
55

66
--- |

‎llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/global-rv64.mir

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
22
# RUN: llc -mtriple=riscv64 -run-pass=regbankselect \
3-
# RUN: -disable-gisel-legality-check -simplify-mir -verify-machineinstrs %s \
3+
# RUN: -simplify-mir -verify-machineinstrs %s \
44
# RUN: -o - | FileCheck -check-prefix=RV64I %s
55

66
--- |

‎llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/load-rv32.mir

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
22
# RUN: llc -mtriple=riscv32 -run-pass=regbankselect \
3-
# RUN: -disable-gisel-legality-check -simplify-mir -verify-machineinstrs %s \
3+
# RUN: -simplify-mir -verify-machineinstrs %s \
44
# RUN: -o - | FileCheck -check-prefix=RV32I %s
55

66
---

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