Skip to content

Commit aec8883

Browse files
MaskRayMaskRay
committed
MC: Remove unneeded MCFixupKind casts
1 parent d575f80 commit aec8883

File tree

15 files changed

+99
-116
lines changed

15 files changed

+99
-116
lines changed

‎llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCCodeEmitter.cpp

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -303,7 +303,7 @@ AArch64MCCodeEmitter::getAddSubImmOpValue(const MCInst &MI, unsigned OpIdx,
303303
const MCExpr *Expr = MO.getExpr();
304304

305305
// Encode the 12 bits of the fixup.
306-
MCFixupKind Kind = MCFixupKind(AArch64::fixup_aarch64_add_imm12);
306+
MCFixupKind Kind = AArch64::fixup_aarch64_add_imm12;
307307
addFixup(Fixups, 0, Expr, Kind);
308308

309309
++MCNumFixups;
@@ -413,8 +413,8 @@ AArch64MCCodeEmitter::getMoveWideImmOpValue(const MCInst &MI, unsigned OpIdx,
413413
return MO.getImm();
414414
assert(MO.isExpr() && "Unexpected movz/movk immediate");
415415

416-
Fixups.push_back(MCFixup::create(0, MO.getExpr(),
417-
MCFixupKind(AArch64::fixup_aarch64_movw)));
416+
Fixups.push_back(
417+
MCFixup::create(0, MO.getExpr(), AArch64::fixup_aarch64_movw));
418418

419419
++MCNumFixups;
420420

‎llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp

Lines changed: 16 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -987,17 +987,17 @@ getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx,
987987
"Thumb mode requires different encoding");
988988
Reg = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
989989
isAdd = false; // 'U' bit is set as part of the fixup.
990-
MCFixupKind Kind = MCFixupKind(ARM::fixup_arm_ldst_abs_12);
990+
MCFixupKind Kind = ARM::fixup_arm_ldst_abs_12;
991991
addFixup(Fixups, 0, MO1.getExpr(), Kind);
992992
}
993993
} else if (MO.isExpr()) {
994994
Reg = CTX.getRegisterInfo()->getEncodingValue(ARM::PC); // Rn is PC.
995995
isAdd = false; // 'U' bit is set as part of the fixup.
996996
MCFixupKind Kind;
997997
if (isThumb2(STI))
998-
Kind = MCFixupKind(ARM::fixup_t2_ldst_pcrel_12);
998+
Kind = ARM::fixup_t2_ldst_pcrel_12;
999999
else
1000-
Kind = MCFixupKind(ARM::fixup_arm_ldst_pcrel_12);
1000+
Kind = ARM::fixup_arm_ldst_pcrel_12;
10011001
addFixup(Fixups, 0, MO.getExpr(), Kind);
10021002

10031003
++MCNumCPRelocations;
@@ -1122,7 +1122,7 @@ getT2AddrModeImm8s4OpValue(const MCInst &MI, unsigned OpIdx,
11221122

11231123
assert(MO.isExpr() && "Unexpected machine operand type!");
11241124
const MCExpr *Expr = MO.getExpr();
1125-
MCFixupKind Kind = MCFixupKind(ARM::fixup_t2_pcrel_10);
1125+
MCFixupKind Kind = ARM::fixup_t2_pcrel_10;
11261126
addFixup(Fixups, 0, Expr, Kind);
11271127

11281128
++MCNumCPRelocations;
@@ -1241,22 +1241,22 @@ uint32_t ARMMCCodeEmitter::getHiLoImmOpValue(const MCInst &MI, unsigned OpIdx,
12411241
case ARM::S_HI_8_15:
12421242
if (!isThumb(STI))
12431243
llvm_unreachable(":upper_8_15: not supported in Arm state");
1244-
Kind = MCFixupKind(ARM::fixup_arm_thumb_upper_8_15);
1244+
Kind = ARM::fixup_arm_thumb_upper_8_15;
12451245
break;
12461246
case ARM::S_HI_0_7:
12471247
if (!isThumb(STI))
12481248
llvm_unreachable(":upper_0_7: not supported in Arm state");
1249-
Kind = MCFixupKind(ARM::fixup_arm_thumb_upper_0_7);
1249+
Kind = ARM::fixup_arm_thumb_upper_0_7;
12501250
break;
12511251
case ARM::S_LO_8_15:
12521252
if (!isThumb(STI))
12531253
llvm_unreachable(":lower_8_15: not supported in Arm state");
1254-
Kind = MCFixupKind(ARM::fixup_arm_thumb_lower_8_15);
1254+
Kind = ARM::fixup_arm_thumb_lower_8_15;
12551255
break;
12561256
case ARM::S_LO_0_7:
12571257
if (!isThumb(STI))
12581258
llvm_unreachable(":lower_0_7: not supported in Arm state");
1259-
Kind = MCFixupKind(ARM::fixup_arm_thumb_lower_0_7);
1259+
Kind = ARM::fixup_arm_thumb_lower_0_7;
12601260
break;
12611261
}
12621262

@@ -1381,7 +1381,7 @@ getAddrMode3OpValue(const MCInst &MI, unsigned OpIdx,
13811381

13821382
assert(MO.isExpr() && "Unexpected machine operand type!");
13831383
const MCExpr *Expr = MO.getExpr();
1384-
MCFixupKind Kind = MCFixupKind(ARM::fixup_arm_pcrel_10_unscaled);
1384+
MCFixupKind Kind = ARM::fixup_arm_pcrel_10_unscaled;
13851385
addFixup(Fixups, 0, Expr, Kind);
13861386

13871387
++MCNumCPRelocations;
@@ -1461,9 +1461,9 @@ getAddrMode5OpValue(const MCInst &MI, unsigned OpIdx,
14611461
const MCExpr *Expr = MO.getExpr();
14621462
MCFixupKind Kind;
14631463
if (isThumb2(STI))
1464-
Kind = MCFixupKind(ARM::fixup_t2_pcrel_10);
1464+
Kind = ARM::fixup_t2_pcrel_10;
14651465
else
1466-
Kind = MCFixupKind(ARM::fixup_arm_pcrel_10);
1466+
Kind = ARM::fixup_arm_pcrel_10;
14671467
addFixup(Fixups, 0, Expr, Kind);
14681468

14691469
++MCNumCPRelocations;
@@ -1501,9 +1501,9 @@ getAddrMode5FP16OpValue(const MCInst &MI, unsigned OpIdx,
15011501
const MCExpr *Expr = MO.getExpr();
15021502
MCFixupKind Kind;
15031503
if (isThumb2(STI))
1504-
Kind = MCFixupKind(ARM::fixup_t2_pcrel_9);
1504+
Kind = ARM::fixup_t2_pcrel_9;
15051505
else
1506-
Kind = MCFixupKind(ARM::fixup_arm_pcrel_9);
1506+
Kind = ARM::fixup_arm_pcrel_9;
15071507
addFixup(Fixups, 0, Expr, Kind);
15081508

15091509
++MCNumCPRelocations;
@@ -1529,7 +1529,7 @@ unsigned ARMMCCodeEmitter::getModImmOpValue(const MCInst &MI, unsigned Op,
15291529
if (MO.isExpr()) {
15301530
const MCExpr *Expr = MO.getExpr();
15311531
// Fixups resolve to plain values that need to be encoded.
1532-
MCFixupKind Kind = MCFixupKind(ARM::fixup_arm_mod_imm);
1532+
MCFixupKind Kind = ARM::fixup_arm_mod_imm;
15331533
addFixup(Fixups, 0, Expr, Kind);
15341534
return 0;
15351535
}
@@ -1547,7 +1547,7 @@ unsigned ARMMCCodeEmitter::getT2SOImmOpValue(const MCInst &MI, unsigned Op,
15471547
if (MO.isExpr()) {
15481548
const MCExpr *Expr = MO.getExpr();
15491549
// Fixups resolve to plain values that need to be encoded.
1550-
MCFixupKind Kind = MCFixupKind(ARM::fixup_t2_so_imm);
1550+
MCFixupKind Kind = ARM::fixup_t2_so_imm;
15511551
addFixup(Fixups, 0, Expr, Kind);
15521552
return 0;
15531553
}
@@ -1995,7 +1995,7 @@ ARMMCCodeEmitter::getBFAfterTargetOpValue(const MCInst &MI, unsigned OpIdx,
19951995
assert(BranchMO.isExpr());
19961996
const MCExpr *DiffExpr = MCBinaryExpr::createSub(
19971997
MO.getExpr(), BranchMO.getExpr(), CTX);
1998-
MCFixupKind Kind = MCFixupKind(ARM::fixup_bfcsel_else_target);
1998+
MCFixupKind Kind = ARM::fixup_bfcsel_else_target;
19991999
addFixup(Fixups, 0, DiffExpr, Kind);
20002000
return 0;
20012001
}

‎llvm/lib/Target/AVR/MCTargetDesc/AVRMCCodeEmitter.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -166,7 +166,7 @@ unsigned AVRMCCodeEmitter::encodeMemri(const MCInst &MI, unsigned OpNo,
166166
OffsetBits = OffsetOp.getImm();
167167
} else if (OffsetOp.isExpr()) {
168168
OffsetBits = 0;
169-
addFixup(Fixups, 0, OffsetOp.getExpr(), MCFixupKind(AVR::fixup_6));
169+
addFixup(Fixups, 0, OffsetOp.getExpr(), AVR::fixup_6);
170170
} else {
171171
llvm_unreachable("Invalid value for offset");
172172
}
@@ -215,7 +215,7 @@ unsigned AVRMCCodeEmitter::encodeCallTarget(const MCInst &MI, unsigned OpNo,
215215
auto MO = MI.getOperand(OpNo);
216216

217217
if (MO.isExpr()) {
218-
MCFixupKind FixupKind = static_cast<MCFixupKind>(AVR::fixup_call);
218+
MCFixupKind FixupKind = AVR::fixup_call;
219219
addFixup(Fixups, 0, MO.getExpr(), FixupKind);
220220
return 0;
221221
}

‎llvm/lib/Target/CSKY/MCTargetDesc/CSKYMCCodeEmitter.cpp

Lines changed: 11 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -176,7 +176,7 @@ class CSKYMCCodeEmitter : public MCCodeEmitter {
176176
const MCOperand &MO = MI.getOperand(Idx);
177177
assert(MO.isExpr() && "Unexpected MO type.");
178178

179-
MCFixupKind Kind = MCFixupKind(CSKY::fixup_csky_pcrel_imm26_scale2);
179+
MCFixupKind Kind = CSKY::fixup_csky_pcrel_imm26_scale2;
180180
if (MO.getExpr()->getKind() == MCExpr::Specifier)
181181
Kind = getTargetFixup(MO.getExpr());
182182

@@ -190,7 +190,7 @@ class CSKYMCCodeEmitter : public MCCodeEmitter {
190190
const MCOperand &MO = MI.getOperand(Idx);
191191
assert(MO.isExpr() && "Unexpected MO type.");
192192

193-
MCFixupKind Kind = MCFixupKind(CSKY::fixup_csky_pcrel_imm18_scale2);
193+
MCFixupKind Kind = CSKY::fixup_csky_pcrel_imm18_scale2;
194194
if (MO.getExpr()->getKind() == MCExpr::Specifier)
195195
Kind = getTargetFixup(MO.getExpr());
196196

@@ -481,23 +481,23 @@ MCFixupKind CSKYMCCodeEmitter::getTargetFixup(const MCExpr *Expr) const {
481481
default:
482482
llvm_unreachable("Unhandled fixup kind!");
483483
case CSKY::S_ADDR:
484-
return MCFixupKind(CSKY::fixup_csky_addr32);
484+
return CSKY::fixup_csky_addr32;
485485
case CSKY::S_ADDR_HI16:
486-
return MCFixupKind(CSKY::fixup_csky_addr_hi16);
486+
return CSKY::fixup_csky_addr_hi16;
487487
case CSKY::S_ADDR_LO16:
488-
return MCFixupKind(CSKY::fixup_csky_addr_lo16);
488+
return CSKY::fixup_csky_addr_lo16;
489489
case CSKY::S_GOT:
490-
return MCFixupKind(CSKY::fixup_csky_got32);
490+
return CSKY::fixup_csky_got32;
491491
case CSKY::S_GOTPC:
492-
return MCFixupKind(CSKY::fixup_csky_gotpc);
492+
return CSKY::fixup_csky_gotpc;
493493
case CSKY::S_GOTOFF:
494-
return MCFixupKind(CSKY::fixup_csky_gotoff);
494+
return CSKY::fixup_csky_gotoff;
495495
case CSKY::S_PLT:
496-
return MCFixupKind(CSKY::fixup_csky_plt32);
496+
return CSKY::fixup_csky_plt32;
497497
case CSKY::S_PLT_IMM18_BY4:
498-
return MCFixupKind(CSKY::fixup_csky_plt_imm18_scale4);
498+
return CSKY::fixup_csky_plt_imm18_scale4;
499499
case CSKY::S_GOT_IMM18_BY4:
500-
return MCFixupKind(CSKY::fixup_csky_got_imm18_scale4);
500+
return CSKY::fixup_csky_got_imm18_scale4;
501501
}
502502
}
503503

‎llvm/lib/Target/Lanai/MCTargetDesc/LanaiMCCodeEmitter.cpp

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -290,8 +290,7 @@ unsigned LanaiMCCodeEmitter::getBranchTargetOpValue(
290290
if (MCOp.isReg() || MCOp.isImm())
291291
return getMachineOpValue(Inst, MCOp, Fixups, SubtargetInfo);
292292

293-
Fixups.push_back(MCFixup::create(
294-
0, MCOp.getExpr(), static_cast<MCFixupKind>(Lanai::FIXUP_LANAI_25)));
293+
Fixups.push_back(MCFixup::create(0, MCOp.getExpr(), Lanai::FIXUP_LANAI_25));
295294

296295
return 0;
297296
}

‎llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchAsmBackend.cpp

Lines changed: 6 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -265,23 +265,17 @@ getRelocPairForSize(unsigned Size) {
265265
default:
266266
llvm_unreachable("unsupported fixup size");
267267
case 6:
268-
return std::make_pair(MCFixupKind(ELF::R_LARCH_ADD6),
269-
MCFixupKind(ELF::R_LARCH_SUB6));
268+
return std::make_pair(ELF::R_LARCH_ADD6, ELF::R_LARCH_SUB6);
270269
case 8:
271-
return std::make_pair(MCFixupKind(ELF::R_LARCH_ADD8),
272-
MCFixupKind(ELF::R_LARCH_SUB8));
270+
return std::make_pair(ELF::R_LARCH_ADD8, ELF::R_LARCH_SUB8);
273271
case 16:
274-
return std::make_pair(MCFixupKind(ELF::R_LARCH_ADD16),
275-
MCFixupKind(ELF::R_LARCH_SUB16));
272+
return std::make_pair(ELF::R_LARCH_ADD16, ELF::R_LARCH_SUB16);
276273
case 32:
277-
return std::make_pair(MCFixupKind(ELF::R_LARCH_ADD32),
278-
MCFixupKind(ELF::R_LARCH_SUB32));
274+
return std::make_pair(ELF::R_LARCH_ADD32, ELF::R_LARCH_SUB32);
279275
case 64:
280-
return std::make_pair(MCFixupKind(ELF::R_LARCH_ADD64),
281-
MCFixupKind(ELF::R_LARCH_SUB64));
276+
return std::make_pair(ELF::R_LARCH_ADD64, ELF::R_LARCH_SUB64);
282277
case 128:
283-
return std::make_pair(MCFixupKind(ELF::R_LARCH_ADD_ULEB128),
284-
MCFixupKind(ELF::R_LARCH_SUB_ULEB128));
278+
return std::make_pair(ELF::R_LARCH_ADD_ULEB128, ELF::R_LARCH_SUB_ULEB128);
285279
}
286280
}
287281

‎llvm/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp

Lines changed: 30 additions & 33 deletions
Original file line numberDiff line numberDiff line change
@@ -357,41 +357,38 @@ std::optional<MCFixupKind> MipsAsmBackend::getFixupKind(StringRef Name) const {
357357
return StringSwitch<std::optional<MCFixupKind>>(Name)
358358
.Case("R_MIPS_NONE", FK_NONE)
359359
.Case("R_MIPS_32", FK_Data_4)
360-
.Case("R_MIPS_CALL_HI16", (MCFixupKind)Mips::fixup_Mips_CALL_HI16)
361-
.Case("R_MIPS_CALL_LO16", (MCFixupKind)Mips::fixup_Mips_CALL_LO16)
362-
.Case("R_MIPS_CALL16", (MCFixupKind)Mips::fixup_Mips_CALL16)
363-
.Case("R_MIPS_GOT16", (MCFixupKind)Mips::fixup_Mips_GOT)
364-
.Case("R_MIPS_GOT_PAGE", (MCFixupKind)Mips::fixup_Mips_GOT_PAGE)
365-
.Case("R_MIPS_GOT_OFST", (MCFixupKind)Mips::fixup_Mips_GOT_OFST)
366-
.Case("R_MIPS_GOT_DISP", (MCFixupKind)Mips::fixup_Mips_GOT_DISP)
367-
.Case("R_MIPS_GOT_HI16", (MCFixupKind)Mips::fixup_Mips_GOT_HI16)
368-
.Case("R_MIPS_GOT_LO16", (MCFixupKind)Mips::fixup_Mips_GOT_LO16)
369-
.Case("R_MIPS_TLS_GOTTPREL", (MCFixupKind)Mips::fixup_Mips_GOTTPREL)
370-
.Case("R_MIPS_TLS_DTPREL_HI16", (MCFixupKind)Mips::fixup_Mips_DTPREL_HI)
371-
.Case("R_MIPS_TLS_DTPREL_LO16", (MCFixupKind)Mips::fixup_Mips_DTPREL_LO)
372-
.Case("R_MIPS_TLS_GD", (MCFixupKind)Mips::fixup_Mips_TLSGD)
373-
.Case("R_MIPS_TLS_LDM", (MCFixupKind)Mips::fixup_Mips_TLSLDM)
374-
.Case("R_MIPS_TLS_TPREL_HI16", (MCFixupKind)Mips::fixup_Mips_TPREL_HI)
375-
.Case("R_MIPS_TLS_TPREL_LO16", (MCFixupKind)Mips::fixup_Mips_TPREL_LO)
376-
.Case("R_MICROMIPS_CALL16", (MCFixupKind)Mips::fixup_MICROMIPS_CALL16)
377-
.Case("R_MICROMIPS_GOT_DISP", (MCFixupKind)Mips::fixup_MICROMIPS_GOT_DISP)
378-
.Case("R_MICROMIPS_GOT_PAGE", (MCFixupKind)Mips::fixup_MICROMIPS_GOT_PAGE)
379-
.Case("R_MICROMIPS_GOT_OFST", (MCFixupKind)Mips::fixup_MICROMIPS_GOT_OFST)
380-
.Case("R_MICROMIPS_GOT16", (MCFixupKind)Mips::fixup_MICROMIPS_GOT16)
381-
.Case("R_MICROMIPS_TLS_GOTTPREL",
382-
(MCFixupKind)Mips::fixup_MICROMIPS_GOTTPREL)
360+
.Case("R_MIPS_CALL_HI16", Mips::fixup_Mips_CALL_HI16)
361+
.Case("R_MIPS_CALL_LO16", Mips::fixup_Mips_CALL_LO16)
362+
.Case("R_MIPS_CALL16", Mips::fixup_Mips_CALL16)
363+
.Case("R_MIPS_GOT16", Mips::fixup_Mips_GOT)
364+
.Case("R_MIPS_GOT_PAGE", Mips::fixup_Mips_GOT_PAGE)
365+
.Case("R_MIPS_GOT_OFST", Mips::fixup_Mips_GOT_OFST)
366+
.Case("R_MIPS_GOT_DISP", Mips::fixup_Mips_GOT_DISP)
367+
.Case("R_MIPS_GOT_HI16", Mips::fixup_Mips_GOT_HI16)
368+
.Case("R_MIPS_GOT_LO16", Mips::fixup_Mips_GOT_LO16)
369+
.Case("R_MIPS_TLS_GOTTPREL", Mips::fixup_Mips_GOTTPREL)
370+
.Case("R_MIPS_TLS_DTPREL_HI16", Mips::fixup_Mips_DTPREL_HI)
371+
.Case("R_MIPS_TLS_DTPREL_LO16", Mips::fixup_Mips_DTPREL_LO)
372+
.Case("R_MIPS_TLS_GD", Mips::fixup_Mips_TLSGD)
373+
.Case("R_MIPS_TLS_LDM", Mips::fixup_Mips_TLSLDM)
374+
.Case("R_MIPS_TLS_TPREL_HI16", Mips::fixup_Mips_TPREL_HI)
375+
.Case("R_MIPS_TLS_TPREL_LO16", Mips::fixup_Mips_TPREL_LO)
376+
.Case("R_MICROMIPS_CALL16", Mips::fixup_MICROMIPS_CALL16)
377+
.Case("R_MICROMIPS_GOT_DISP", Mips::fixup_MICROMIPS_GOT_DISP)
378+
.Case("R_MICROMIPS_GOT_PAGE", Mips::fixup_MICROMIPS_GOT_PAGE)
379+
.Case("R_MICROMIPS_GOT_OFST", Mips::fixup_MICROMIPS_GOT_OFST)
380+
.Case("R_MICROMIPS_GOT16", Mips::fixup_MICROMIPS_GOT16)
381+
.Case("R_MICROMIPS_TLS_GOTTPREL", Mips::fixup_MICROMIPS_GOTTPREL)
383382
.Case("R_MICROMIPS_TLS_DTPREL_HI16",
384-
(MCFixupKind)Mips::fixup_MICROMIPS_TLS_DTPREL_HI16)
383+
Mips::fixup_MICROMIPS_TLS_DTPREL_HI16)
385384
.Case("R_MICROMIPS_TLS_DTPREL_LO16",
386-
(MCFixupKind)Mips::fixup_MICROMIPS_TLS_DTPREL_LO16)
387-
.Case("R_MICROMIPS_TLS_GD", (MCFixupKind)Mips::fixup_MICROMIPS_TLS_GD)
388-
.Case("R_MICROMIPS_TLS_LDM", (MCFixupKind)Mips::fixup_MICROMIPS_TLS_LDM)
389-
.Case("R_MICROMIPS_TLS_TPREL_HI16",
390-
(MCFixupKind)Mips::fixup_MICROMIPS_TLS_TPREL_HI16)
391-
.Case("R_MICROMIPS_TLS_TPREL_LO16",
392-
(MCFixupKind)Mips::fixup_MICROMIPS_TLS_TPREL_LO16)
393-
.Case("R_MIPS_JALR", (MCFixupKind)Mips::fixup_Mips_JALR)
394-
.Case("R_MICROMIPS_JALR", (MCFixupKind)Mips::fixup_MICROMIPS_JALR)
385+
Mips::fixup_MICROMIPS_TLS_DTPREL_LO16)
386+
.Case("R_MICROMIPS_TLS_GD", Mips::fixup_MICROMIPS_TLS_GD)
387+
.Case("R_MICROMIPS_TLS_LDM", Mips::fixup_MICROMIPS_TLS_LDM)
388+
.Case("R_MICROMIPS_TLS_TPREL_HI16", Mips::fixup_MICROMIPS_TLS_TPREL_HI16)
389+
.Case("R_MICROMIPS_TLS_TPREL_LO16", Mips::fixup_MICROMIPS_TLS_TPREL_LO16)
390+
.Case("R_MIPS_JALR", Mips::fixup_Mips_JALR)
391+
.Case("R_MICROMIPS_JALR", Mips::fixup_MICROMIPS_JALR)
395392
.Default(MCAsmBackend::getFixupKind(Name));
396393
}
397394

‎llvm/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -744,7 +744,7 @@ unsigned MipsMCCodeEmitter::getImmOpValue(const MCInst &MI, const MCOperand &MO,
744744
return Res;
745745
unsigned MIFrm = MipsII::getFormat(MCII.get(MI.getOpcode()).TSFlags);
746746
if (!isa<MCSpecifierExpr>(Expr) && MIFrm == MipsII::FrmI) {
747-
addFixup(Fixups, 0, Expr, MCFixupKind(Mips::fixup_Mips_AnyImm16));
747+
addFixup(Fixups, 0, Expr, Mips::fixup_Mips_AnyImm16);
748748
return 0;
749749
}
750750
return getExprOpValue(Expr, Fixups, STI);

‎llvm/lib/Target/Mips/MCTargetDesc/MipsTargetStreamer.cpp

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -1035,42 +1035,42 @@ MCELFStreamer &MipsTargetELFStreamer::getStreamer() {
10351035
void MipsTargetELFStreamer::emitGPRel32Value(const MCExpr *Value) {
10361036
MCDataFragment *DF = getStreamer().getOrCreateDataFragment();
10371037
DF->addFixup(MCFixup::create(DF->getContents().size(), Value,
1038-
MCFixupKind(Mips::fixup_Mips_GPREL32)));
1038+
Mips::fixup_Mips_GPREL32));
10391039
DF->appendContents(4, 0);
10401040
}
10411041

10421042
void MipsTargetELFStreamer::emitGPRel64Value(const MCExpr *Value) {
10431043
MCDataFragment *DF = getStreamer().getOrCreateDataFragment();
10441044
DF->addFixup(MCFixup::create(DF->getContents().size(), Value,
1045-
MCFixupKind(Mips::fixup_Mips_GPREL32)));
1045+
Mips::fixup_Mips_GPREL32));
10461046
DF->appendContents(8, 0);
10471047
}
10481048

10491049
void MipsTargetELFStreamer::emitDTPRel32Value(const MCExpr *Value) {
10501050
MCDataFragment *DF = getStreamer().getOrCreateDataFragment();
10511051
DF->addFixup(MCFixup::create(DF->getContents().size(), Value,
1052-
MCFixupKind(Mips::fixup_Mips_DTPREL32)));
1052+
Mips::fixup_Mips_DTPREL32));
10531053
DF->appendContents(4, 0);
10541054
}
10551055

10561056
void MipsTargetELFStreamer::emitDTPRel64Value(const MCExpr *Value) {
10571057
MCDataFragment *DF = getStreamer().getOrCreateDataFragment();
10581058
DF->addFixup(MCFixup::create(DF->getContents().size(), Value,
1059-
MCFixupKind(Mips::fixup_Mips_DTPREL64)));
1059+
Mips::fixup_Mips_DTPREL64));
10601060
DF->appendContents(8, 0);
10611061
}
10621062

10631063
void MipsTargetELFStreamer::emitTPRel32Value(const MCExpr *Value) {
10641064
MCDataFragment *DF = getStreamer().getOrCreateDataFragment();
10651065
DF->addFixup(MCFixup::create(DF->getContents().size(), Value,
1066-
MCFixupKind(Mips::fixup_Mips_TPREL32)));
1066+
Mips::fixup_Mips_TPREL32));
10671067
DF->appendContents(4, 0);
10681068
}
10691069

10701070
void MipsTargetELFStreamer::emitTPRel64Value(const MCExpr *Value) {
10711071
MCDataFragment *DF = getStreamer().getOrCreateDataFragment();
10721072
DF->addFixup(MCFixup::create(DF->getContents().size(), Value,
1073-
MCFixupKind(Mips::fixup_Mips_TPREL64)));
1073+
Mips::fixup_Mips_TPREL64));
10741074
DF->appendContents(8, 0);
10751075
}
10761076

‎llvm/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -288,7 +288,7 @@ ELFPPCAsmBackend::getFixupKind(StringRef Name) const {
288288
std::optional<MCFixupKind>
289289
XCOFFPPCAsmBackend::getFixupKind(StringRef Name) const {
290290
return StringSwitch<std::optional<MCFixupKind>>(Name)
291-
.Case("R_REF", (MCFixupKind)PPC::fixup_ppc_nofixup)
291+
.Case("R_REF", PPC::fixup_ppc_nofixup)
292292
.Default(std::nullopt);
293293
}
294294

0 commit comments

Comments
 (0)