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[RISCV] Add initial batch of test coverage for zvqdotq codegen
This is not complete coverage, but it's a starting point for working on codegen for this extension.
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‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-zvqdotq.ll

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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | FileCheck %s
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; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s
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; RUN: llc -mtriple=riscv32 -mattr=+v,+experimental-zvqdotq -verify-machineinstrs < %s | FileCheck %s
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; RUN: llc -mtriple=riscv64 -mattr=+v,+experimental-zvqdotq -verify-machineinstrs < %s | FileCheck %s
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define i32 @vqdot_vv(<16 x i8> %a, <16 x i8> %b) {
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; CHECK-LABEL: vqdot_vv:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma
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; CHECK-NEXT: vsext.vf2 v12, v8
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; CHECK-NEXT: vsext.vf2 v14, v9
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; CHECK-NEXT: vwmul.vv v8, v12, v14
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; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma
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; CHECK-NEXT: vmv.s.x v12, zero
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; CHECK-NEXT: vredsum.vs v8, v8, v12
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; CHECK-NEXT: vmv.x.s a0, v8
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; CHECK-NEXT: ret
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entry:
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%a.sext = sext <16 x i8> %a to <16 x i32>
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%b.sext = sext <16 x i8> %b to <16 x i32>
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%mul = mul nuw nsw <16 x i32> %a.sext, %b.sext
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%res = tail call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> %mul)
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ret i32 %res
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}
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define i32 @vqdot_vx_constant(<16 x i8> %a) {
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; CHECK-LABEL: vqdot_vx_constant:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma
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; CHECK-NEXT: vsext.vf2 v12, v8
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; CHECK-NEXT: li a0, 23
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; CHECK-NEXT: vwmul.vx v8, v12, a0
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; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma
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; CHECK-NEXT: vmv.s.x v12, zero
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; CHECK-NEXT: vredsum.vs v8, v8, v12
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; CHECK-NEXT: vmv.x.s a0, v8
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; CHECK-NEXT: ret
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entry:
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%a.sext = sext <16 x i8> %a to <16 x i32>
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%mul = mul nuw nsw <16 x i32> %a.sext, splat (i32 23)
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%res = tail call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> %mul)
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ret i32 %res
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}
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define i32 @vqdot_vx_constant_swapped(<16 x i8> %a) {
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; CHECK-LABEL: vqdot_vx_constant_swapped:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma
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; CHECK-NEXT: vsext.vf2 v12, v8
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; CHECK-NEXT: li a0, 23
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; CHECK-NEXT: vwmul.vx v8, v12, a0
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; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma
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; CHECK-NEXT: vmv.s.x v12, zero
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; CHECK-NEXT: vredsum.vs v8, v8, v12
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; CHECK-NEXT: vmv.x.s a0, v8
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; CHECK-NEXT: ret
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entry:
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%a.sext = sext <16 x i8> %a to <16 x i32>
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%mul = mul nuw nsw <16 x i32> splat (i32 23), %a.sext
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%res = tail call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> %mul)
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ret i32 %res
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}
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define i32 @vqdotu_vv(<16 x i8> %a, <16 x i8> %b) {
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; CHECK-LABEL: vqdotu_vv:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
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; CHECK-NEXT: vwmulu.vv v10, v8, v9
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; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma
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; CHECK-NEXT: vmv.s.x v8, zero
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; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma
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; CHECK-NEXT: vwredsumu.vs v8, v10, v8
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; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma
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; CHECK-NEXT: vmv.x.s a0, v8
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; CHECK-NEXT: ret
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entry:
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%a.zext = zext <16 x i8> %a to <16 x i32>
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%b.zext = zext <16 x i8> %b to <16 x i32>
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%mul = mul nuw nsw <16 x i32> %a.zext, %b.zext
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%res = tail call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> %mul)
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ret i32 %res
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}
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define i32 @vqdotu_vx_constant(<16 x i8> %a) {
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; CHECK-LABEL: vqdotu_vx_constant:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma
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; CHECK-NEXT: vzext.vf2 v12, v8
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; CHECK-NEXT: li a0, 123
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; CHECK-NEXT: vwmulu.vx v8, v12, a0
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; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma
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; CHECK-NEXT: vmv.s.x v12, zero
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; CHECK-NEXT: vredsum.vs v8, v8, v12
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; CHECK-NEXT: vmv.x.s a0, v8
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; CHECK-NEXT: ret
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entry:
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%a.zext = zext <16 x i8> %a to <16 x i32>
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%mul = mul nuw nsw <16 x i32> %a.zext, splat (i32 123)
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%res = tail call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> %mul)
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ret i32 %res
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}
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define i32 @vqdotsu_vv(<16 x i8> %a, <16 x i8> %b) {
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; CHECK-LABEL: vqdotsu_vv:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma
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; CHECK-NEXT: vsext.vf2 v12, v8
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; CHECK-NEXT: vzext.vf2 v14, v9
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; CHECK-NEXT: vwmulsu.vv v8, v12, v14
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; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma
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; CHECK-NEXT: vmv.s.x v12, zero
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; CHECK-NEXT: vredsum.vs v8, v8, v12
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; CHECK-NEXT: vmv.x.s a0, v8
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; CHECK-NEXT: ret
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entry:
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%a.sext = sext <16 x i8> %a to <16 x i32>
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%b.zext = zext <16 x i8> %b to <16 x i32>
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%mul = mul nuw nsw <16 x i32> %a.sext, %b.zext
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%res = tail call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> %mul)
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ret i32 %res
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}
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define i32 @vqdotsu_vv_swapped(<16 x i8> %a, <16 x i8> %b) {
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; CHECK-LABEL: vqdotsu_vv_swapped:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma
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; CHECK-NEXT: vsext.vf2 v12, v8
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; CHECK-NEXT: vzext.vf2 v14, v9
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; CHECK-NEXT: vwmulsu.vv v8, v12, v14
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; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma
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; CHECK-NEXT: vmv.s.x v12, zero
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; CHECK-NEXT: vredsum.vs v8, v8, v12
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; CHECK-NEXT: vmv.x.s a0, v8
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; CHECK-NEXT: ret
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entry:
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%a.sext = sext <16 x i8> %a to <16 x i32>
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%b.zext = zext <16 x i8> %b to <16 x i32>
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%mul = mul nuw nsw <16 x i32> %b.zext, %a.sext
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%res = tail call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> %mul)
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ret i32 %res
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}
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define i32 @vdotqsu_vx_constant(<16 x i8> %a) {
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; CHECK-LABEL: vdotqsu_vx_constant:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma
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; CHECK-NEXT: vsext.vf2 v12, v8
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; CHECK-NEXT: li a0, 123
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; CHECK-NEXT: vwmul.vx v8, v12, a0
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; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma
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; CHECK-NEXT: vmv.s.x v12, zero
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; CHECK-NEXT: vredsum.vs v8, v8, v12
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; CHECK-NEXT: vmv.x.s a0, v8
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; CHECK-NEXT: ret
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entry:
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%a.sext = sext <16 x i8> %a to <16 x i32>
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%mul = mul nuw nsw <16 x i32> %a.sext, splat (i32 123)
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%res = tail call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> %mul)
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ret i32 %res
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}
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define i32 @vdotqus_vx_constant(<16 x i8> %a) {
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; CHECK-LABEL: vdotqus_vx_constant:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma
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; CHECK-NEXT: vzext.vf2 v12, v8
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; CHECK-NEXT: li a0, -23
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; CHECK-NEXT: vmv.v.x v14, a0
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; CHECK-NEXT: vwmulsu.vv v8, v14, v12
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; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma
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; CHECK-NEXT: vmv.s.x v12, zero
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; CHECK-NEXT: vredsum.vs v8, v8, v12
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; CHECK-NEXT: vmv.x.s a0, v8
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; CHECK-NEXT: ret
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entry:
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%a.zext = zext <16 x i8> %a to <16 x i32>
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%mul = mul nuw nsw <16 x i32> %a.zext, splat (i32 -23)
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%res = tail call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> %mul)
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ret i32 %res
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}
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define i32 @reduce_of_sext(<16 x i8> %a) {
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; CHECK-LABEL: reduce_of_sext:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma
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; CHECK-NEXT: vsext.vf4 v12, v8
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; CHECK-NEXT: vmv.s.x v8, zero
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; CHECK-NEXT: vredsum.vs v8, v12, v8
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; CHECK-NEXT: vmv.x.s a0, v8
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; CHECK-NEXT: ret
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entry:
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%a.ext = sext <16 x i8> %a to <16 x i32>
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%res = tail call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> %a.ext)
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ret i32 %res
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}
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define i32 @reduce_of_zext(<16 x i8> %a) {
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; CHECK-LABEL: reduce_of_zext:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma
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; CHECK-NEXT: vzext.vf4 v12, v8
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; CHECK-NEXT: vmv.s.x v8, zero
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; CHECK-NEXT: vredsum.vs v8, v12, v8
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; CHECK-NEXT: vmv.x.s a0, v8
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; CHECK-NEXT: ret
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entry:
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%a.ext = zext <16 x i8> %a to <16 x i32>
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%res = tail call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> %a.ext)
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ret i32 %res
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}

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