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4vtomat4vtomat
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fixup! [RISCV][VLS] Support RISCV VLS calling convention
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4 files changed

+44
-18
lines changed

4 files changed

+44
-18
lines changed

‎clang/lib/CodeGen/Targets/RISCV.cpp

Lines changed: 9 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -114,8 +114,13 @@ void RISCVABIInfo::appendAttributeMangling(StringRef AttrStr,
114114

115115
void RISCVABIInfo::computeInfo(CGFunctionInfo &FI) const {
116116
unsigned ArgABIVLen = 1 << FI.getExtInfo().getLog2RISCVABIVLen();
117-
if (ArgABIVLen == 1)
117+
// If ArgABIVLen is default value(2), try to set it to the value passed by
118+
// option if any, otherwise, set it to default value 128.
119+
// Note that ArgABIVLen == 1 means vector_cc is not enabled.
120+
if (ArgABIVLen == 2 && ABIVLen)
118121
ArgABIVLen = ABIVLen;
122+
else if (ArgABIVLen == 2)
123+
ArgABIVLen = 128;
119124

120125
QualType RetTy = FI.getReturnType();
121126
if (!getCXXABI().classifyReturnType(FI))
@@ -416,8 +421,8 @@ ABIArgInfo RISCVABIInfo::coerceVLSVector(QualType Ty,
416421
(EltType->isDoubleTy() && !TI.hasFeature("zve64d")) ||
417422
(EltType->isIntegerTy(64) && !TI.hasFeature("zve64x")) ||
418423
EltType->isIntegerTy(128)) {
419-
NumElts = NumElts * EltType->getScalarSizeInBits() / 32;
420-
EltType = llvm::Type::getInt32Ty(getVMContext());
424+
EltType =
425+
llvm::Type::getIntNTy(getVMContext(), EltType->getScalarSizeInBits());
421426
}
422427

423428
// Generic vector
@@ -537,7 +542,7 @@ ABIArgInfo RISCVABIInfo::classifyArgumentType(QualType Ty, bool IsFixed,
537542
VT->getVectorKind() == VectorKind::RVVFixedLengthMask_2 ||
538543
VT->getVectorKind() == VectorKind::RVVFixedLengthMask_4)
539544
return coerceVLSVector(Ty);
540-
if (VT->getVectorKind() == VectorKind::Generic && ArgABIVLen != 0)
545+
if (VT->getVectorKind() == VectorKind::Generic && ArgABIVLen != 1)
541546
// Generic vector without riscv_vls_cc should fall through and pass by
542547
// reference.
543548
return coerceVLSVector(Ty, ArgABIVLen);

‎clang/lib/Sema/SemaType.cpp

Lines changed: 4 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -8107,12 +8107,13 @@ static bool handleFunctionTypeAttr(TypeProcessingState &state, ParsedAttr &attr,
81078107
Attr *CCAttr = getCCTypeAttr(S.Context, attr);
81088108

81098109
if (attr.getKind() == ParsedAttr::AT_RISCVVLSCC) {
8110-
// If the riscv_abi_vlen doesn't have any argument, default ABI_VLEN is 128.
8111-
unsigned ABIVLen = 128;
8110+
// If the riscv_abi_vlen doesn't have any argument, we set set it to 2 to
8111+
// differentiate from functions without attribute.
8112+
unsigned ABIVLen = 2;
81128113
if (attr.getNumArgs() &&
81138114
!S.checkUInt32Argument(attr, attr.getArgAsExpr(0), ABIVLen))
81148115
return false;
8115-
if (ABIVLen < 32 || ABIVLen > 65536) {
8116+
if (ABIVLen != 2 && (ABIVLen < 32 || ABIVLen > 65536)) {
81168117
S.Diag(attr.getLoc(), diag::err_argument_invalid_range)
81178118
<< ABIVLen << 32 << 65536;
81188119
return false;

‎clang/test/CodeGen/RISCV/riscv-vector-callingconv-llvm-ir.c

Lines changed: 19 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -1,10 +1,14 @@
11
// REQUIRES: riscv-registered-target
22
// RUN: %clang_cc1 -triple riscv64 -target-feature +v \
33
// RUN: -emit-llvm %s -o - | FileCheck -check-prefix=CHECK-LLVM %s
4+
// RUN: %clang_cc1 -triple riscv64 -target-feature +zve32x \
5+
// RUN: -emit-llvm %s -o - | FileCheck -check-prefix=CHECK-LLVM-ZVE32X %s
46
// RUN: %clang_cc1 -std=c23 -triple riscv64 -target-feature +v \
57
// RUN: -emit-llvm %s -o - | FileCheck -check-prefix=CHECK-LLVM %s
68
// RUN: %clang_cc1 -triple riscv64 -mriscv-abi-vlen=256 -target-feature +v \
79
// RUN: -emit-llvm %s -o - | FileCheck -check-prefix=CHECK-LLVM-ABI-VLEN %s
10+
// RUN: %clang_cc1 -triple riscv64 -mriscv-abi-vlen=256 -target-feature +zve32x \
11+
// RUN: -emit-llvm %s -o - | FileCheck -check-prefix=CHECK-LLVM-ABI-VLEN-ZVE32X %s
812
// RUN: %clang_cc1 -std=c23 -triple riscv64 -mriscv-abi-vlen=256 -target-feature +v \
913
// RUN: -emit-llvm %s -o - | FileCheck -check-prefix=CHECK-LLVM-ABI-VLEN %s
1014

@@ -38,25 +42,33 @@ vint32m1_t test_no_vector_cc_attr(vint32m1_t input, int32_t *base, size_t vl) {
3842
}
3943

4044
// CHECK-LLVM: define dso_local void @test_vls_no_cc(i128 noundef %arg.coerce)
41-
// CHECK-LLVM-ABI-VLEN: define dso_local void @test_vls_no_cc(<vscale x 1 x i32> noundef %arg.coerce)
45+
// CHECK-LLVM-ABI-VLEN: define dso_local void @test_vls_no_cc(i128 noundef %arg.coerce)
4246
void test_vls_no_cc(__attribute__((vector_size(16))) int arg) {}
4347

4448
// CHECK-LLVM: define dso_local riscv_vls_cc void @test_vls_default_abi_vlen(<vscale x 2 x i32> noundef %arg.coerce)
45-
// CHECK-LLVM-ABI-VLEN: define dso_local riscv_vls_cc void @test_vls_default_abi_vlen(<vscale x 2 x i32> noundef %arg.coerce)
49+
// CHECK-LLVM-ABI-VLEN: define dso_local riscv_vls_cc void @test_vls_default_abi_vlen(<vscale x 1 x i32> noundef %arg.coerce)
4650
void __attribute__((riscv_vls_cc)) test_vls_default_abi_vlen(__attribute__((vector_size(16))) int arg) {}
4751

4852
// CHECK-LLVM: define dso_local riscv_vls_cc void @test_vls_default_abi_vlen_c23(<vscale x 2 x i32> noundef %arg.coerce)
49-
// CHECK-LLVM-ABI-VLEN: define dso_local riscv_vls_cc void @test_vls_default_abi_vlen_c23(<vscale x 2 x i32> noundef %arg.coerce)
53+
// CHECK-LLVM-ABI-VLEN: define dso_local riscv_vls_cc void @test_vls_default_abi_vlen_c23(<vscale x 1 x i32> noundef %arg.coerce)
5054
[[riscv::vls_cc]] void test_vls_default_abi_vlen_c23(__attribute__((vector_size(16))) int arg) {}
5155

52-
// CHECK-LLVM: define dso_local riscv_vls_cc void @test_vls_default_abi_vlen_unsupported_feature(<vscale x 2 x i32> noundef %arg.coerce)
53-
// CHECK-LLVM-ABI-VLEN: define dso_local riscv_vls_cc void @test_vls_default_abi_vlen_unsupported_feature(<vscale x 2 x i32> noundef %arg.coerce)
56+
// CHECK-LLVM: define dso_local riscv_vls_cc void @test_vls_default_abi_vlen_unsupported_feature(<vscale x 4 x i16> noundef %arg.coerce)
57+
// CHECK-LLVM-ABI-VLEN: define dso_local riscv_vls_cc void @test_vls_default_abi_vlen_unsupported_feature(<vscale x 2 x i16> noundef %arg.coerce)
5458
void __attribute__((riscv_vls_cc)) test_vls_default_abi_vlen_unsupported_feature(__attribute__((vector_size(16))) _Float16 arg) {}
5559

56-
// CHECK-LLVM: define dso_local riscv_vls_cc void @test_vls_default_abi_vlen_c23_unsupported_feature(<vscale x 2 x i32> noundef %arg.coerce)
57-
// CHECK-LLVM-ABI-VLEN: define dso_local riscv_vls_cc void @test_vls_default_abi_vlen_c23_unsupported_feature(<vscale x 2 x i32> noundef %arg.coerce)
60+
// CHECK-LLVM: define dso_local riscv_vls_cc void @test_vls_default_abi_vlen_c23_unsupported_feature(<vscale x 4 x i16> noundef %arg.coerce)
61+
// CHECK-LLVM-ABI-VLEN: define dso_local riscv_vls_cc void @test_vls_default_abi_vlen_c23_unsupported_feature(<vscale x 2 x i16> noundef %arg.coerce)
5862
[[riscv::vls_cc]] void test_vls_default_abi_vlen_c23_unsupported_feature(__attribute__((vector_size(16))) _Float16 arg) {}
5963

64+
// CHECK-LLVM-ZVE32X: define dso_local riscv_vls_cc void @test_vls_default_abi_vlen_unsupported_feature_zve32x(<vscale x 2 x i32> noundef %arg.coerce)
65+
// CHECK-LLVM-ABI-VLEN-ZVE32X: define dso_local riscv_vls_cc void @test_vls_default_abi_vlen_unsupported_feature_zve32x(<vscale x 1 x i32> noundef %arg.coerce)
66+
void __attribute__((riscv_vls_cc)) test_vls_default_abi_vlen_unsupported_feature_zve32x(__attribute__((vector_size(16))) float arg) {}
67+
68+
// CHECK-LLVM-ZVE32X: define dso_local riscv_vls_cc void @test_vls_default_abi_vlen_c23_unsupported_feature_zve32x(<vscale x 2 x i32> noundef %arg.coerce)
69+
// CHECK-LLVM-ABI-VLEN-ZVE32X: define dso_local riscv_vls_cc void @test_vls_default_abi_vlen_c23_unsupported_feature_zve32x(<vscale x 1 x i32> noundef %arg.coerce)
70+
[[riscv::vls_cc]] void test_vls_default_abi_vlen_c23_unsupported_feature_zve32x(__attribute__((vector_size(16))) float arg) {}
71+
6072
// CHECK-LLVM: define dso_local riscv_vls_cc void @test_vls_256_abi_vlen(<vscale x 1 x i32> noundef %arg.coerce)
6173
// CHECK-LLVM-ABI-VLEN: define dso_local riscv_vls_cc void @test_vls_256_abi_vlen(<vscale x 1 x i32> noundef %arg.coerce)
6274
void __attribute__((riscv_vls_cc(256))) test_vls_256_abi_vlen(__attribute__((vector_size(16))) int arg) {}

‎clang/test/CodeGen/RISCV/riscv-vector-callingconv-llvm-ir.cpp

Lines changed: 12 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1,8 +1,12 @@
11
// REQUIRES: riscv-registered-target
22
// RUN: %clang_cc1 -std=c++11 -triple riscv64 -target-feature +v \
33
// RUN: -emit-llvm %s -o - | FileCheck -check-prefix=CHECK-LLVM %s
4+
// RUN: %clang_cc1 -std=c++11 -triple riscv64 -target-feature +zve32x \
5+
// RUN: -emit-llvm %s -o - | FileCheck -check-prefix=CHECK-LLVM-ZVE32X %s
46
// RUN: %clang_cc1 -std=c++11 -triple riscv64 -mriscv-abi-vlen=256 -target-feature +v \
57
// RUN: -emit-llvm %s -o - | FileCheck -check-prefix=CHECK-LLVM-ABI-VLEN %s
8+
// RUN: %clang_cc1 -std=c++11 -triple riscv64 -mriscv-abi-vlen=256 -target-feature +zve32x \
9+
// RUN: -emit-llvm %s -o - | FileCheck -check-prefix=CHECK-LLVM-ABI-VLEN-ZVE32X %s
610

711
#include <riscv_vector.h>
812

@@ -34,17 +38,21 @@ vint32m1_t test_no_vector_cc_attr(vint32m1_t input, int32_t *base, size_t vl) {
3438
}
3539

3640
// CHECK-LLVM: define dso_local void @_Z14test_vls_no_ccDv4_i(i128 noundef %arg.coerce)
37-
// CHECK-LLVM-ABI-VLEN: define dso_local void @_Z14test_vls_no_ccDv4_i(<vscale x 1 x i32> noundef %arg.coerce)
41+
// CHECK-LLVM-ABI-VLEN: define dso_local void @_Z14test_vls_no_ccDv4_i(i128 noundef %arg.coerce)
3842
void test_vls_no_cc(__attribute__((vector_size(16))) int arg) {}
3943

4044
// CHECK-LLVM: define dso_local riscv_vls_cc void @_Z25test_vls_default_abi_vlenDv4_i(<vscale x 2 x i32> noundef %arg.coerce)
41-
// CHECK-LLVM-ABI-VLEN: define dso_local riscv_vls_cc void @_Z25test_vls_default_abi_vlenDv4_i(<vscale x 2 x i32> noundef %arg.coerce)
45+
// CHECK-LLVM-ABI-VLEN: define dso_local riscv_vls_cc void @_Z25test_vls_default_abi_vlenDv4_i(<vscale x 1 x i32> noundef %arg.coerce)
4246
[[riscv::vls_cc]] void test_vls_default_abi_vlen(__attribute__((vector_size(16))) int arg) {}
4347

44-
// CHECK-LLVM: define dso_local riscv_vls_cc void @_Z45test_vls_default_abi_vlen_unsupported_featureDv8_DF16_(<vscale x 2 x i32> noundef %arg.coerce)
45-
// CHECK-LLVM-ABI-VLEN: define dso_local riscv_vls_cc void @_Z45test_vls_default_abi_vlen_unsupported_featureDv8_DF16_(<vscale x 2 x i32> noundef %arg.coerce)
48+
// CHECK-LLVM: define dso_local riscv_vls_cc void @_Z45test_vls_default_abi_vlen_unsupported_featureDv8_DF16_(<vscale x 4 x i16> noundef %arg.coerce)
49+
// CHECK-LLVM-ABI-VLEN: define dso_local riscv_vls_cc void @_Z45test_vls_default_abi_vlen_unsupported_featureDv8_DF16_(<vscale x 2 x i16> noundef %arg.coerce)
4650
[[riscv::vls_cc]] void test_vls_default_abi_vlen_unsupported_feature(__attribute__((vector_size(16))) _Float16 arg) {}
4751

52+
// CHECK-LLVM-ZVE32X: define dso_local riscv_vls_cc void @_Z52test_vls_default_abi_vlen_unsupported_feature_zve32xDv4_f(<vscale x 2 x i32> noundef %arg.coerce)
53+
// CHECK-LLVM-ABI-VLEN-ZVE32X: define dso_local riscv_vls_cc void @_Z52test_vls_default_abi_vlen_unsupported_feature_zve32xDv4_f(<vscale x 1 x i32> noundef %arg.coerce)
54+
[[riscv::vls_cc]] void test_vls_default_abi_vlen_unsupported_feature_zve32x(__attribute__((vector_size(16))) float arg) {}
55+
4856
// CHECK-LLVM: define dso_local riscv_vls_cc void @_Z21test_vls_256_abi_vlenDv4_i(<vscale x 1 x i32> noundef %arg.coerce)
4957
// CHECK-LLVM-ABI-VLEN: define dso_local riscv_vls_cc void @_Z21test_vls_256_abi_vlenDv4_i(<vscale x 1 x i32> noundef %arg.coerce)
5058
[[riscv::vls_cc(256)]] void test_vls_256_abi_vlen(__attribute__((vector_size(16))) int arg) {}

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