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davemgreendavemgreen
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[ARM][AArch64] Clean up some v3float intrinsic definitions
We have had some v3float definitions sneak in and some functions were incorrectly named after #146691. Use v3f32 instead.
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-28
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3 files changed

+29
-28
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‎llvm/test/CodeGen/AArch64/extract-vector-elt.ll

Lines changed: 20 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -331,7 +331,7 @@ define float @extract_v4i32_minimum(<4 x float> %a, <4 x float> %b, i32 %c) {
331331
; CHECK-GI-NEXT: add sp, sp, #16
332332
; CHECK-GI-NEXT: ret
333333
entry:
334-
%vector = call <4 x float> @llvm.minimum.v4float(<4 x float> %a, <4 x float> %b)
334+
%vector = call <4 x float> @llvm.minimum.v4f32(<4 x float> %a, <4 x float> %b)
335335
%d = extractelement <4 x float> %vector, i32 %c
336336
ret float %d
337337
}
@@ -367,7 +367,7 @@ define float @extract_v4i32_minimum_build_vector(<4 x float> %a, <4 x float> %b,
367367
; CHECK-GI-NEXT: add sp, sp, #16
368368
; CHECK-GI-NEXT: ret
369369
entry:
370-
%vector = call <4 x float> @llvm.minimum.v4float(<4 x float> %a, <4 x float> <float 42.0, float 11.0, float 17.0, float 6.0>)
370+
%vector = call <4 x float> @llvm.minimum.v4f32(<4 x float> %a, <4 x float> <float 42.0, float 11.0, float 17.0, float 6.0>)
371371
%d = extractelement <4 x float> %vector, i32 %c
372372
ret float %d
373373
}
@@ -381,7 +381,7 @@ define float @extract_v4i32_minimum_build_vector_const(<4 x float> %a, <4 x floa
381381
; CHECK-NEXT: mov s0, v0.s[1]
382382
; CHECK-NEXT: ret
383383
entry:
384-
%vector = call <4 x float> @llvm.minimum.v4float(<4 x float> %a, <4 x float> <float 42.0, float 11.0, float 17.0, float 6.0>)
384+
%vector = call <4 x float> @llvm.minimum.v4f32(<4 x float> %a, <4 x float> <float 42.0, float 11.0, float 17.0, float 6.0>)
385385
%d = extractelement <4 x float> %vector, i32 1
386386
ret float %d
387387
}
@@ -414,7 +414,7 @@ define float @extract_v4i32_copysign_build_vector(<4 x float> %a, <4 x float> %b
414414
; CHECK-GI-NEXT: add sp, sp, #16
415415
; CHECK-GI-NEXT: ret
416416
entry:
417-
%vector = call <4 x float> @llvm.copysign.v4float(<4 x float> %a, <4 x float> <float 42.0, float 11.0, float 17.0, float 6.0>)
417+
%vector = call <4 x float> @llvm.copysign.v4f32(<4 x float> %a, <4 x float> <float 42.0, float 11.0, float 17.0, float 6.0>)
418418
%d = extractelement <4 x float> %vector, i32 %c
419419
ret float %d
420420
}
@@ -433,7 +433,7 @@ define float @extract_v4i32_copysign_build_vector_const(<4 x float> %a, <4 x flo
433433
; CHECK-GI-NEXT: mov s0, v0.s[2]
434434
; CHECK-GI-NEXT: ret
435435
entry:
436-
%vector = call <4 x float> @llvm.copysign.v4float(<4 x float> %a, <4 x float> <float 42.0, float 11.0, float 17.0, float 6.0>)
436+
%vector = call <4 x float> @llvm.copysign.v4f32(<4 x float> %a, <4 x float> <float 42.0, float 11.0, float 17.0, float 6.0>)
437437
%d = extractelement <4 x float> %vector, i32 2
438438
ret float %d
439439
}
@@ -508,8 +508,8 @@ entry:
508508
ret i32 %d
509509
}
510510

511-
define i32 @extract_v4float_fcmp(<4 x float> %a, <4 x float> %b, i32 %c) {
512-
; CHECK-SD-LABEL: extract_v4float_fcmp:
511+
define i32 @extract_v4f32_fcmp(<4 x float> %a, <4 x float> %b, i32 %c) {
512+
; CHECK-SD-LABEL: extract_v4f32_fcmp:
513513
; CHECK-SD: // %bb.0: // %entry
514514
; CHECK-SD-NEXT: sub sp, sp, #16
515515
; CHECK-SD-NEXT: .cfi_def_cfa_offset 16
@@ -524,7 +524,7 @@ define i32 @extract_v4float_fcmp(<4 x float> %a, <4 x float> %b, i32 %c) {
524524
; CHECK-SD-NEXT: add sp, sp, #16
525525
; CHECK-SD-NEXT: ret
526526
;
527-
; CHECK-GI-LABEL: extract_v4float_fcmp:
527+
; CHECK-GI-LABEL: extract_v4f32_fcmp:
528528
; CHECK-GI: // %bb.0: // %entry
529529
; CHECK-GI-NEXT: sub sp, sp, #16
530530
; CHECK-GI-NEXT: .cfi_def_cfa_offset 16
@@ -548,16 +548,16 @@ entry:
548548
ret i32 %d
549549
}
550550

551-
define i32 @extract_v4float_fcmp_const(<4 x float> %a, <4 x float> %b, i32 %c) {
552-
; CHECK-SD-LABEL: extract_v4float_fcmp_const:
551+
define i32 @extract_v4f32_fcmp_const(<4 x float> %a, <4 x float> %b, i32 %c) {
552+
; CHECK-SD-LABEL: extract_v4f32_fcmp_const:
553553
; CHECK-SD: // %bb.0: // %entry
554554
; CHECK-SD-NEXT: movi v1.4s, #1
555555
; CHECK-SD-NEXT: fcmeq v0.4s, v0.4s, v0.4s
556556
; CHECK-SD-NEXT: bic v0.16b, v1.16b, v0.16b
557557
; CHECK-SD-NEXT: mov w0, v0.s[1]
558558
; CHECK-SD-NEXT: ret
559559
;
560-
; CHECK-GI-LABEL: extract_v4float_fcmp_const:
560+
; CHECK-GI-LABEL: extract_v4f32_fcmp_const:
561561
; CHECK-GI: // %bb.0: // %entry
562562
; CHECK-GI-NEXT: fmov v1.4s, #1.00000000
563563
; CHECK-GI-NEXT: fcmge v2.4s, v0.4s, v1.4s
@@ -680,9 +680,9 @@ define i32 @extract_v4i32_abs(<4 x float> %a, i32 %c) {
680680
; CHECK-GI-NEXT: add sp, sp, #16
681681
; CHECK-GI-NEXT: ret
682682
entry:
683-
%ceil = call <4 x float> @llvm.ceil.v4float(<4 x float> %a)
684-
%floor = call <4 x float> @llvm.floor.v4float(<4 x float> %ceil)
685-
%fabs = call <4 x float> @llvm.fabs.v4float(<4 x float> %floor)
683+
%ceil = call <4 x float> @llvm.ceil.v4f32(<4 x float> %a)
684+
%floor = call <4 x float> @llvm.floor.v4f32(<4 x float> %ceil)
685+
%fabs = call <4 x float> @llvm.fabs.v4f32(<4 x float> %floor)
686686
%abs = fptosi <4 x float> %fabs to <4 x i32>
687687
%vector = call <4 x i32> @llvm.abs.v4i32(<4 x i32> %abs, i1 0)
688688
%d = extractelement <4 x i32> %vector, i32 %c
@@ -708,9 +708,9 @@ define i32 @extract_v4i32_abs_const(<4 x float> %a, i32 %c) {
708708
; CHECK-GI-NEXT: fmov w0, s0
709709
; CHECK-GI-NEXT: ret
710710
entry:
711-
%ceil = call <4 x float> @llvm.ceil.v4float(<4 x float> <float 1.0, float 4.0, float 3.0, float 2.0>)
712-
%floor = call <4 x float> @llvm.floor.v4float(<4 x float> %ceil)
713-
%fabs = call <4 x float> @llvm.fabs.v4float(<4 x float> %floor)
711+
%ceil = call <4 x float> @llvm.ceil.v4f32(<4 x float> <float 1.0, float 4.0, float 3.0, float 2.0>)
712+
%floor = call <4 x float> @llvm.floor.v4f32(<4 x float> %ceil)
713+
%fabs = call <4 x float> @llvm.fabs.v4f32(<4 x float> %floor)
714714
%abs = fptosi <4 x float> %fabs to <4 x i32>
715715
%vector = call <4 x i32> @llvm.abs.v4i32(<4 x i32> %abs, i1 0)
716716
%d = extractelement <4 x i32> %vector, i32 1
@@ -751,9 +751,9 @@ define i32 @extract_v4i32_abs_half_const(<4 x float> %a, i32 %c) {
751751
; CHECK-GI-NEXT: add sp, sp, #16
752752
; CHECK-GI-NEXT: ret
753753
entry:
754-
%ceil = call <4 x float> @llvm.ceil.v4float(<4 x float> <float 1.0, float 4.0, float 3.0, float 2.0>)
755-
%floor = call <4 x float> @llvm.floor.v4float(<4 x float> %ceil)
756-
%fabs = call <4 x float> @llvm.fabs.v4float(<4 x float> %floor)
754+
%ceil = call <4 x float> @llvm.ceil.v4f32(<4 x float> <float 1.0, float 4.0, float 3.0, float 2.0>)
755+
%floor = call <4 x float> @llvm.floor.v4f32(<4 x float> %ceil)
756+
%fabs = call <4 x float> @llvm.fabs.v4f32(<4 x float> %floor)
757757
%abs = fptosi <4 x float> %fabs to <4 x i32>
758758
%vector = call <4 x i32> @llvm.abs.v4i32(<4 x i32> %abs, i1 0)
759759
%d = extractelement <4 x i32> %vector, i32 %c

‎llvm/test/CodeGen/AArch64/llvm.frexp.ll

Lines changed: 6 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,7 @@
11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
22
; RUN: llc -mtriple=aarch64-gnu-linux < %s | FileCheck -check-prefixes=CHECK %s
33
; RUN: llc -mtriple=aarch64-windows-pc-msvc < %s | FileCheck -check-prefixes=WINDOWS %s
4+
45
define { half, i32 } @test_frexp_f16_i32(half %a) {
56
; CHECK-LABEL: test_frexp_f16_i32:
67
; CHECK: // %bb.0:
@@ -391,8 +392,8 @@ define <2 x i32> @test_frexp_v2f16_v2i32_only_use_exp(<2 x half> %a) {
391392
ret <2 x i32> %result.1
392393
}
393394

394-
define { <3 x float>, <3 x i32> } @test_frexp_v3f16_v3i32(<3 x float> %a) {
395-
; CHECK-LABEL: test_frexp_v3f16_v3i32:
395+
define { <3 x float>, <3 x i32> } @test_frexp_v3f32_v3i32(<3 x float> %a) {
396+
; CHECK-LABEL: test_frexp_v3f32_v3i32:
396397
; CHECK: // %bb.0:
397398
; CHECK-NEXT: sub sp, sp, #80
398399
; CHECK-NEXT: str x30, [sp, #48] // 8-byte Folded Spill
@@ -433,8 +434,8 @@ define { <3 x float>, <3 x i32> } @test_frexp_v3f16_v3i32(<3 x float> %a) {
433434
; CHECK-NEXT: add sp, sp, #80
434435
; CHECK-NEXT: ret
435436
;
436-
; WINDOWS-LABEL: test_frexp_v3f16_v3i32:
437-
; WINDOWS: .seh_proc test_frexp_v3f16_v3i32
437+
; WINDOWS-LABEL: test_frexp_v3f32_v3i32:
438+
; WINDOWS: .seh_proc test_frexp_v3f32_v3i32
438439
; WINDOWS-NEXT: // %bb.0:
439440
; WINDOWS-NEXT: sub sp, sp, #80
440441
; WINDOWS-NEXT: .seh_stackalloc 80
@@ -493,7 +494,7 @@ define { <3 x float>, <3 x i32> } @test_frexp_v3f16_v3i32(<3 x float> %a) {
493494
; WINDOWS-NEXT: ret
494495
; WINDOWS-NEXT: .seh_endfunclet
495496
; WINDOWS-NEXT: .seh_endproc
496-
%result = call { <3 x float>, <3 x i32> } @llvm.frexp.v3float.v3i32(<3 x float> %a)
497+
%result = call { <3 x float>, <3 x i32> } @llvm.frexp.v3f32.v3i32(<3 x float> %a)
497498
ret { <3 x float>, <3 x i32> } %result
498499
}
499500

‎llvm/test/CodeGen/ARM/llvm.frexp.ll

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -141,8 +141,8 @@ define <2 x i32> @test_frexp_v2f16_v2i32_only_use_exp(<2 x half> %a) {
141141
ret <2 x i32> %result.1
142142
}
143143

144-
define { <3 x float>, <3 x i32> } @test_frexp_v3f16_v3i32(<3 x float> %a) {
145-
; CHECK-LABEL: test_frexp_v3f16_v3i32:
144+
define { <3 x float>, <3 x i32> } @test_frexp_v3f32_v3i32(<3 x float> %a) {
145+
; CHECK-LABEL: test_frexp_v3f32_v3i32:
146146
; CHECK: @ %bb.0:
147147
; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, lr}
148148
; CHECK-NEXT: vpush {d8, d9}
@@ -174,7 +174,7 @@ define { <3 x float>, <3 x i32> } @test_frexp_v3f16_v3i32(<3 x float> %a) {
174174
; CHECK-NEXT: add sp, #8
175175
; CHECK-NEXT: vpop {d8, d9}
176176
; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, pc}
177-
%result = call { <3 x float>, <3 x i32> } @llvm.frexp.v3float.v3i32(<3 x float> %a)
177+
%result = call { <3 x float>, <3 x i32> } @llvm.frexp.v3f32.v3i32(<3 x float> %a)
178178
ret { <3 x float>, <3 x i32> } %result
179179
}
180180

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