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‎llvm/lib/Target/AMDGPU/AMDGPURegBankCombiner.cpp

Lines changed: 4 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -416,6 +416,10 @@ bool AMDGPURegBankCombinerImpl::lowerUniformBFX(MachineInstr &MI) const {
416416
? (Signed ? AMDGPU::S_BFE_I32 : AMDGPU::S_BFE_U32)
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: (Signed ? AMDGPU::S_BFE_I64 : AMDGPU::S_BFE_U64);
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// Pack the offset and width of a BFE into
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// the format expected by the S_BFE_I32 / S_BFE_U32. In the second
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// source, bits [5:0] contain the offset and bits [22:16] the width.
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// Ensure the high bits are clear to insert the offset.
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auto OffsetMask = B.buildConstant(S32, maskTrailingOnes<unsigned>(6));
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auto ClampOffset = B.buildAnd(S32, OffsetReg, OffsetMask);
@@ -424,9 +428,6 @@ bool AMDGPURegBankCombinerImpl::lowerUniformBFX(MachineInstr &MI) const {
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auto ShiftAmt = B.buildConstant(S32, 16);
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auto ShiftWidth = B.buildShl(S32, WidthReg, ShiftAmt);
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427-
// Transformation function, pack the offset and width of a BFE into
428-
// the format expected by the S_BFE_I32 / S_BFE_U32. In the second
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// source, bits [5:0] contain the offset and bits [22:16] the width.
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auto MergedInputs = B.buildOr(S32, ClampOffset, ShiftWidth);
431432

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MRI.setRegBank(OffsetMask.getReg(0), *RB);

‎llvm/test/CodeGen/AMDGPU/GlobalISel/regbankcombiner-lower-bfx.mir

Lines changed: 107 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,107 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -run-pass=amdgpu-regbank-combiner -verify-machineinstrs %s -o - | FileCheck %s
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---
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name: test_s_bfe_i32__constants
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.1:
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liveins: $sgpr0
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; CHECK-LABEL: name: test_s_bfe_i32__constants
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; CHECK: liveins: $sgpr0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: %reg:sreg_32(s32) = COPY $sgpr0
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; CHECK-NEXT: %width:sgpr(s32) = G_CONSTANT i32 5
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; CHECK-NEXT: %offset:sgpr(s32) = G_CONSTANT i32 7
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; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 16
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; CHECK-NEXT: [[SHL:%[0-9]+]]:sgpr(s32) = G_SHL %width, [[C]](s32)
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; CHECK-NEXT: [[OR:%[0-9]+]]:sreg_32(s32) = G_OR %offset, [[SHL]]
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; CHECK-NEXT: %bfx:sreg_32(s32) = S_BFE_I32 %reg(s32), [[OR]](s32), implicit-def $scc
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; CHECK-NEXT: $sgpr0 = COPY %bfx(s32)
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%reg:sgpr(s32) = COPY $sgpr0
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%width:sgpr(s32) = G_CONSTANT i32 5
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%offset:sgpr(s32) = G_CONSTANT i32 7
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%bfx:sgpr(s32) = G_SBFX %reg, %offset, %width
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$sgpr0 = COPY %bfx
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...
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---
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name: test_s_bfe_u32__constants
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.1:
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liveins: $sgpr0
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; CHECK-LABEL: name: test_s_bfe_u32__constants
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; CHECK: liveins: $sgpr0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: %reg:sreg_32(s32) = COPY $sgpr0
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; CHECK-NEXT: %width:sgpr(s32) = G_CONSTANT i32 5
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; CHECK-NEXT: %offset:sgpr(s32) = G_CONSTANT i32 7
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; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 16
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; CHECK-NEXT: [[SHL:%[0-9]+]]:sgpr(s32) = G_SHL %width, [[C]](s32)
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; CHECK-NEXT: [[OR:%[0-9]+]]:sreg_32(s32) = G_OR %offset, [[SHL]]
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; CHECK-NEXT: %bfx:sreg_32(s32) = S_BFE_U32 %reg(s32), [[OR]](s32), implicit-def $scc
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; CHECK-NEXT: $sgpr0 = COPY %bfx(s32)
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%reg:sgpr(s32) = COPY $sgpr0
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%width:sgpr(s32) = G_CONSTANT i32 5
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%offset:sgpr(s32) = G_CONSTANT i32 7
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%bfx:sgpr(s32) = G_UBFX %reg, %offset, %width
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$sgpr0 = COPY %bfx
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...
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---
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name: test_s_bfe_i64__constants
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.1:
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liveins: $sgpr0_sgpr1
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; CHECK-LABEL: name: test_s_bfe_i64__constants
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; CHECK: liveins: $sgpr0_sgpr1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: %reg:sreg_64(s64) = COPY $sgpr0_sgpr1
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; CHECK-NEXT: %width:sgpr(s32) = G_CONSTANT i32 5
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; CHECK-NEXT: %offset:sgpr(s32) = G_CONSTANT i32 7
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; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 16
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; CHECK-NEXT: [[SHL:%[0-9]+]]:sgpr(s32) = G_SHL %width, [[C]](s32)
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; CHECK-NEXT: [[OR:%[0-9]+]]:sreg_32(s32) = G_OR %offset, [[SHL]]
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; CHECK-NEXT: %bfx:sreg_64(s64) = S_BFE_I64 %reg(s64), [[OR]](s32), implicit-def $scc
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; CHECK-NEXT: $sgpr0_sgpr1 = COPY %bfx(s64)
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%reg:sgpr(s64) = COPY $sgpr0_sgpr1
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%width:sgpr(s32) = G_CONSTANT i32 5
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%offset:sgpr(s32) = G_CONSTANT i32 7
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%bfx:sgpr(s64) = G_SBFX %reg, %offset, %width
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$sgpr0_sgpr1 = COPY %bfx
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...
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---
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name: test_s_bfe_u64__constants
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.1:
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liveins: $sgpr0_sgpr1
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; CHECK-LABEL: name: test_s_bfe_u64__constants
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; CHECK: liveins: $sgpr0_sgpr1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: %reg:sreg_64(s64) = COPY $sgpr0_sgpr1
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; CHECK-NEXT: %width:sgpr(s32) = G_CONSTANT i32 5
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; CHECK-NEXT: %offset:sgpr(s32) = G_CONSTANT i32 7
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; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 16
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; CHECK-NEXT: [[SHL:%[0-9]+]]:sgpr(s32) = G_SHL %width, [[C]](s32)
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; CHECK-NEXT: [[OR:%[0-9]+]]:sreg_32(s32) = G_OR %offset, [[SHL]]
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; CHECK-NEXT: %bfx:sreg_64(s64) = S_BFE_U64 %reg(s64), [[OR]](s32), implicit-def $scc
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; CHECK-NEXT: $sgpr0_sgpr1 = COPY %bfx(s64)
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%reg:sgpr(s64) = COPY $sgpr0_sgpr1
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%width:sgpr(s32) = G_CONSTANT i32 5
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%offset:sgpr(s32) = G_CONSTANT i32 7
105+
%bfx:sgpr(s64) = G_UBFX %reg, %offset, %width
106+
$sgpr0_sgpr1 = COPY %bfx
107+
...

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