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1 parent e0a812f commit 972fd20Copy full SHA for 972fd20
llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
@@ -1440,10 +1440,14 @@ bool NVPTXDAGToDAGISel::tryStore(SDNode *N) {
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MVT ScalarVT = SimpleVT.getScalarType();
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unsigned ToTypeWidth = ScalarVT.getSizeInBits();
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if (SimpleVT.isVector()) {
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- assert((Isv2x16VT(StoreVT) || StoreVT == MVT::v4i8) &&
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- "Unexpected vector type");
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- // v2x16 is stored using st.b32
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- ToTypeWidth = 32;
+ if (Isv2x16VT(StoreVT) || StoreVT == MVT::v4i8)
+ // v2x16 is stored using st.b32
+ ToTypeWidth = 32;
+ else if (StoreVT == MVT::v2f32)
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+ // v2f32 is stored using st.b64
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+ ToTypeWidth = 64;
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+ else
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+ llvm_unreachable("Unexpected vector type");
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}
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unsigned int ToType = getLdStRegType(ScalarVT);
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