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[LegalizeTypes] Reuse Op1 and Op2 variables to hold promoted values in PromoteIntRes_ADDSUBSHLSAT. NFC (#102840)
We don't need the original values after we promote them.
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llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp

Lines changed: 9 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -1078,15 +1078,14 @@ SDValue DAGTypeLegalizer::PromoteIntRes_ADDSUBSHLSAT(SDNode *N) {
10781078
bool IsShift = Opcode == ISD::USHLSAT || Opcode == ISD::SSHLSAT;
10791079

10801080
// FIXME: We need vp-aware PromotedInteger functions.
1081-
SDValue Op1Promoted, Op2Promoted;
10821081
if (IsShift) {
1083-
Op1Promoted = GetPromotedInteger(Op1);
1084-
Op2Promoted = ZExtPromotedInteger(Op2);
1082+
Op1 = GetPromotedInteger(Op1);
1083+
Op2 = ZExtPromotedInteger(Op2);
10851084
} else {
1086-
Op1Promoted = SExtPromotedInteger(Op1);
1087-
Op2Promoted = SExtPromotedInteger(Op2);
1085+
Op1 = SExtPromotedInteger(Op1);
1086+
Op2 = SExtPromotedInteger(Op2);
10881087
}
1089-
EVT PromotedType = Op1Promoted.getValueType();
1088+
EVT PromotedType = Op1.getValueType();
10901089
unsigned NewBits = PromotedType.getScalarSizeInBits();
10911090

10921091
// Shift cannot use a min/max expansion, we can't detect overflow if all of
@@ -1110,14 +1109,11 @@ SDValue DAGTypeLegalizer::PromoteIntRes_ADDSUBSHLSAT(SDNode *N) {
11101109
unsigned SHLAmount = NewBits - OldBits;
11111110
SDValue ShiftAmount =
11121111
DAG.getShiftAmountConstant(SHLAmount, PromotedType, dl);
1113-
Op1Promoted =
1114-
DAG.getNode(ISD::SHL, dl, PromotedType, Op1Promoted, ShiftAmount);
1112+
Op1 = DAG.getNode(ISD::SHL, dl, PromotedType, Op1, ShiftAmount);
11151113
if (!IsShift)
1116-
Op2Promoted =
1117-
matcher.getNode(ISD::SHL, dl, PromotedType, Op2Promoted, ShiftAmount);
1114+
Op2 = matcher.getNode(ISD::SHL, dl, PromotedType, Op2, ShiftAmount);
11181115

1119-
SDValue Result =
1120-
matcher.getNode(Opcode, dl, PromotedType, Op1Promoted, Op2Promoted);
1116+
SDValue Result = matcher.getNode(Opcode, dl, PromotedType, Op1, Op2);
11211117
return matcher.getNode(ShiftOp, dl, PromotedType, Result, ShiftAmount);
11221118
}
11231119

@@ -1126,8 +1122,7 @@ SDValue DAGTypeLegalizer::PromoteIntRes_ADDSUBSHLSAT(SDNode *N) {
11261122
APInt MaxVal = APInt::getSignedMaxValue(OldBits).sext(NewBits);
11271123
SDValue SatMin = DAG.getConstant(MinVal, dl, PromotedType);
11281124
SDValue SatMax = DAG.getConstant(MaxVal, dl, PromotedType);
1129-
SDValue Result =
1130-
matcher.getNode(AddOp, dl, PromotedType, Op1Promoted, Op2Promoted);
1125+
SDValue Result = matcher.getNode(AddOp, dl, PromotedType, Op1, Op2);
11311126
Result = matcher.getNode(ISD::SMIN, dl, PromotedType, Result, SatMax);
11321127
Result = matcher.getNode(ISD::SMAX, dl, PromotedType, Result, SatMin);
11331128
return Result;

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