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[OpenMP] Enable simd in non-reduction composite constructs (#146097)
Despite currently being ignored with a warning, simd as a leaf in composite constructs behaves as expected when the construct does not contain a reduction. Enable it for those non-reduction constructs. --------- Signed-off-by: Kajetan Puchalski <kajetan.puchalski@arm.com>
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4 files changed

+133
-19
lines changed

4 files changed

+133
-19
lines changed

‎mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp

Lines changed: 4 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -2852,11 +2852,10 @@ convertOmpSimd(Operation &opInst, llvm::IRBuilderBase &builder,
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llvm::OpenMPIRBuilder *ompBuilder = moduleTranslation.getOpenMPBuilder();
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auto simdOp = cast<omp::SimdOp>(opInst);
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2855-
// TODO: Replace this with proper composite translation support.
2856-
// Currently, simd information on composite constructs is ignored, so e.g.
2857-
// 'do/for simd' will be treated the same as a standalone 'do/for'. This is
2858-
// allowed by the spec, since it's equivalent to using a SIMD length of 1.
2859-
if (simdOp.isComposite()) {
2855+
// Ignore simd in composite constructs with unsupported clauses
2856+
// TODO: Replace this once simd + clause combinations are properly supported
2857+
if (simdOp.isComposite() &&
2858+
(simdOp.getReductionByref().has_value() || simdOp.getIfExpr())) {
28602859
if (failed(convertIgnoredWrapper(simdOp, moduleTranslation)))
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return failure();
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‎mlir/test/Target/LLVMIR/openmp-parallel-do-simd.mlir

Lines changed: 38 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,38 @@
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// RUN: mlir-translate -mlir-to-llvmir %s | FileCheck %s
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// Check that omp.simd as a leaf of a composite construct still generates
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// the appropriate loop vectorization attribute.
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// CHECK-LABEL: define internal void @test_parallel_do_simd..omp_par
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// CHECK: omp.par.entry:
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// CHECK: omp.par.region:
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// CHECK: omp_loop.header:
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// CHECK: omp_loop.inc:
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// CHECK-NEXT: %omp_loop.next = add nuw i32 %omp_loop.iv, 1
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// CHECK-NEXT: br label %omp_loop.header, !llvm.loop ![[LOOP_ATTR:.*]]
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// CHECK: ![[LOOP_ATTR]] = distinct !{![[LOOP_ATTR]], ![[LPAR:.*]], ![[LVEC:.*]]}
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// CHECK: ![[LPAR]] = !{!"llvm.loop.parallel_accesses", ![[PAR_ACC:.*]]}
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// CHECK: ![[LVEC]] = !{!"llvm.loop.vectorize.enable", i1 true}
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llvm.func @test_parallel_do_simd() {
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%0 = llvm.mlir.constant(1 : i64) : i64
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%1 = llvm.alloca %0 x i32 {bindc_name = "i"} : (i64) -> !llvm.ptr
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%2 = llvm.mlir.constant(1000 : i32) : i32
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%3 = llvm.mlir.constant(1 : i32) : i32
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%4 = llvm.mlir.constant(1 : i64) : i64
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omp.parallel {
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%5 = llvm.mlir.constant(1 : i64) : i64
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%6 = llvm.alloca %5 x i32 {bindc_name = "i", pinned} : (i64) -> !llvm.ptr
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%7 = llvm.mlir.constant(1 : i64) : i64
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omp.wsloop {
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omp.simd {
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omp.loop_nest (%arg0) : i32 = (%3) to (%2) inclusive step (%3) {
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llvm.store %arg0, %6 : i32, !llvm.ptr
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omp.yield
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}
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} {omp.composite}
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} {omp.composite}
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omp.terminator
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}
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llvm.return
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}

‎mlir/test/Target/LLVMIR/openmp-teams-distribute-parallel-do-simd.mlir

Lines changed: 51 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,51 @@
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// RUN: mlir-translate --mlir-to-llvmir %s | FileCheck %s
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// Check that omp.simd as a leaf of a composite construct still generates
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// the appropriate loop vectorization attribute.
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// CHECK-LABEL: define internal void @test_teams_distribute_parallel_do_simd..omp_par.2
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// CHECK: teams.body:
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// CHECK: omp.teams.region:
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// CHECK-LABEL: define internal void @test_teams_distribute_parallel_do_simd..omp_par.1
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// CHECK: omp.par.entry:
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// CHECK: omp.par.region:
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// CHECK: distribute.exit:
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// CHECK-LABEL: define internal void @test_teams_distribute_parallel_do_simd..omp_par
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// CHECK: distribute.body:
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// CHECK: omp.distribute.region:
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// CHECK: omp_loop.header:
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// CHECK: omp_loop.inc:
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// CHECK-NEXT: %omp_loop.next = add nuw i32 %omp_loop.iv, 1
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// CHECK-NEXT: br label %omp_loop.header, !llvm.loop ![[LOOP_ATTR:.*]]
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// CHECK: ![[LOOP_ATTR]] = distinct !{![[LOOP_ATTR]], ![[LPAR:.*]], ![[LVEC:.*]]}
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// CHECK: ![[LPAR]] = !{!"llvm.loop.parallel_accesses", ![[PAR_ACC:.*]]}
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// CHECK: ![[LVEC]] = !{!"llvm.loop.vectorize.enable", i1 true}
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omp.private {type = private} @_QFEi_private_i32 : i32
28+
llvm.func @test_teams_distribute_parallel_do_simd() {
29+
%0 = llvm.mlir.constant(1 : i64) : i64
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%1 = llvm.alloca %0 x i32 {bindc_name = "i"} : (i64) -> !llvm.ptr
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%2 = llvm.mlir.constant(1000 : i32) : i32
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%3 = llvm.mlir.constant(1 : i32) : i32
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%4 = llvm.mlir.constant(1 : i64) : i64
34+
omp.teams {
35+
omp.parallel {
36+
omp.distribute {
37+
omp.wsloop {
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omp.simd private(@_QFEi_private_i32 %1 -> %arg0 : !llvm.ptr) {
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omp.loop_nest (%arg1) : i32 = (%3) to (%2) inclusive step (%3) {
40+
llvm.store %arg1, %arg0 : i32, !llvm.ptr
41+
omp.yield
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}
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} {omp.composite}
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} {omp.composite}
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} {omp.composite}
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omp.terminator
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} {omp.composite}
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omp.terminator
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}
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llvm.return
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}

‎mlir/test/Target/LLVMIR/openmp-todo.mlir

Lines changed: 40 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -26,20 +26,6 @@ llvm.func @atomic_hint(%v : !llvm.ptr, %x : !llvm.ptr, %expr : i32) {
2626

2727
// -----
2828

29-
llvm.func @do_simd(%lb : i32, %ub : i32, %step : i32) {
30-
omp.wsloop {
31-
// expected-warning@below {{simd information on composite construct discarded}}
32-
omp.simd {
33-
omp.loop_nest (%iv) : i32 = (%lb) to (%ub) step (%step) {
34-
omp.yield
35-
}
36-
} {omp.composite}
37-
} {omp.composite}
38-
llvm.return
39-
}
40-
41-
// -----
42-
4329
llvm.func @distribute_allocate(%lb : i32, %ub : i32, %step : i32, %x : !llvm.ptr) {
4430
// expected-error@below {{not yet implemented: Unhandled clause allocate in omp.distribute operation}}
4531
// expected-error@below {{LLVM Translation failed for operation: omp.distribute}}
@@ -503,3 +489,43 @@ llvm.func @wsloop_order(%lb : i32, %ub : i32, %step : i32) {
503489
}
504490
llvm.return
505491
}
492+
493+
// -----
494+
495+
llvm.func @do_simd_if(%1 : !llvm.ptr, %5 : i32, %4 : i32, %6 : i1) {
496+
omp.wsloop {
497+
// expected-warning@below {{simd information on composite construct discarded}}
498+
omp.simd if(%6) {
499+
omp.loop_nest (%arg0) : i32 = (%5) to (%4) inclusive step (%5) {
500+
llvm.store %arg0, %1 : i32, !llvm.ptr
501+
omp.yield
502+
}
503+
} {omp.composite}
504+
} {omp.composite}
505+
llvm.return
506+
}
507+
508+
// -----
509+
510+
omp.declare_reduction @add_reduction_i32 : i32 init {
511+
^bb0(%arg0: i32):
512+
%0 = llvm.mlir.constant(0 : i32) : i32
513+
omp.yield(%0 : i32)
514+
} combiner {
515+
^bb0(%arg0: i32, %arg1: i32):
516+
%0 = llvm.add %arg0, %arg1 : i32
517+
omp.yield(%0 : i32)
518+
}
519+
llvm.func @do_simd_reduction(%1 : !llvm.ptr, %3 : !llvm.ptr, %6 : i32, %7 : i32) {
520+
omp.wsloop reduction(@add_reduction_i32 %3 -> %arg0 : !llvm.ptr) {
521+
// expected-warning@below {{simd information on composite construct discarded}}
522+
omp.simd reduction(@add_reduction_i32 %arg0 -> %arg1 : !llvm.ptr) {
523+
omp.loop_nest (%arg2) : i32 = (%7) to (%6) inclusive step (%7) {
524+
llvm.store %arg2, %1 : i32, !llvm.ptr
525+
%12 = llvm.load %arg1 : !llvm.ptr -> i32
526+
omp.yield
527+
}
528+
} {omp.composite}
529+
} {omp.composite}
530+
llvm.return
531+
}

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