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-28
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2 files changed

+27
-28
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llvm/lib/Target/AArch64/AArch64FrameLowering.cpp

Lines changed: 24 additions & 25 deletions
Original file line numberDiff line numberDiff line change
@@ -4382,8 +4382,8 @@ determineSVEStackObjectOffsets(MachineFunction &MF, bool AssignOffsets,
43824382
// With SplitSVEObjects we maintain separate stack offsets for predicates
43834383
// (PPRs) and SVE vectors (ZPRs). When SplitSVEObjects is disabled predicates
43844384
// are included in the SVE vector area.
4385-
int64_t &ZPROffset = SVEStack.ZPRStackSize;
4386-
int64_t &PPROffset =
4385+
uint64_t &ZPRStackTop = SVEStack.ZPRStackSize;
4386+
uint64_t &PPRStackTop =
43874387
SplitSVEObjects ? SVEStack.PPRStackSize : SVEStack.ZPRStackSize;
43884388

43894389
#ifndef NDEBUG
@@ -4394,10 +4394,10 @@ determineSVEStackObjectOffsets(MachineFunction &MF, bool AssignOffsets,
43944394
"reference.");
43954395
#endif
43964396

4397-
auto OffsetForObject = [&](int FI, int64_t &ZPROffset,
4398-
int64_t &PPROffset) -> int64_t & {
4399-
return MFI.getStackID(FI) == TargetStackID::ScalableVector ? ZPROffset
4400-
: PPROffset;
4397+
auto StackForObject = [&](int FI, uint64_t &ZPRStackTop,
4398+
uint64_t &PPRStackTop) -> uint64_t & {
4399+
return MFI.getStackID(FI) == TargetStackID::ScalableVector ? ZPRStackTop
4400+
: PPRStackTop;
44014401
};
44024402

44034403
auto Assign = [&MFI](int FI, int64_t Offset) {
@@ -4409,19 +4409,17 @@ determineSVEStackObjectOffsets(MachineFunction &MF, bool AssignOffsets,
44094409
int MinCSFrameIndex, MaxCSFrameIndex;
44104410
if (getSVECalleeSaveSlotRange(MFI, MinCSFrameIndex, MaxCSFrameIndex)) {
44114411
for (int FI = MinCSFrameIndex; FI <= MaxCSFrameIndex; ++FI) {
4412-
int64_t &Offset = OffsetForObject(FI, ZPROffset, PPROffset);
4413-
Offset += MFI.getObjectSize(FI);
4414-
Offset = alignTo(Offset, MFI.getObjectAlign(FI));
4415-
if (AssignOffsets) {
4416-
LLVM_DEBUG(dbgs() << "FI: " << FI << ", Offset: " << -Offset << "\n");
4417-
Assign(FI, -Offset);
4418-
}
4412+
uint64_t &StackTop = StackForObject(FI, ZPRStackTop, PPRStackTop);
4413+
StackTop += MFI.getObjectSize(FI);
4414+
StackTop = alignTo(StackTop, MFI.getObjectAlign(FI));
4415+
if (AssignOffsets)
4416+
Assign(FI, -int64_t(StackTop));
44194417
}
44204418
}
44214419

44224420
// Ensure the CS area is 16-byte aligned.
4423-
PPROffset = alignTo(PPROffset, Align(16U));
4424-
ZPROffset = alignTo(ZPROffset, Align(16U));
4421+
PPRStackTop = alignTo(PPRStackTop, Align(16U));
4422+
ZPRStackTop = alignTo(ZPRStackTop, Align(16U));
44254423

44264424
// Create a buffer of SVE objects to allocate and sort it.
44274425
SmallVector<int, 8> ObjectsToAllocate;
@@ -4458,14 +4456,14 @@ determineSVEStackObjectOffsets(MachineFunction &MF, bool AssignOffsets,
44584456
report_fatal_error(
44594457
"Alignment of scalable vectors > 16 bytes is not yet supported");
44604458

4461-
int64_t &Offset = OffsetForObject(FI, ZPROffset, PPROffset);
4462-
Offset = alignTo(Offset + MFI.getObjectSize(FI), Alignment);
4459+
uint64_t &StackTop = StackForObject(FI, ZPRStackTop, PPRStackTop);
4460+
StackTop = alignTo(StackTop + MFI.getObjectSize(FI), Alignment);
44634461
if (AssignOffsets)
4464-
Assign(FI, -Offset);
4462+
Assign(FI, -int64_t(StackTop));
44654463
}
44664464

4467-
PPROffset = alignTo(PPROffset, Align(16U));
4468-
ZPROffset = alignTo(ZPROffset, Align(16U));
4465+
PPRStackTop = alignTo(PPRStackTop, Align(16U));
4466+
ZPRStackTop = alignTo(ZPRStackTop, Align(16U));
44694467
return SVEStack;
44704468
}
44714469

@@ -4474,9 +4472,11 @@ AArch64FrameLowering::estimateSVEStackObjectOffsets(MachineFunction &MF) const {
44744472
return determineSVEStackObjectOffsets(MF, false);
44754473
}
44764474

4477-
SVEStackSizes
4478-
AArch64FrameLowering::assignSVEStackObjectOffsets(MachineFunction &MF) const {
4479-
return determineSVEStackObjectOffsets(MF, true);
4475+
void AArch64FrameLowering::assignSVEStackObjectOffsets(
4476+
MachineFunction &MF) const {
4477+
auto [ZPRStackSize, PPRStackSize] = determineSVEStackObjectOffsets(MF, true);
4478+
MF.getInfo<AArch64FunctionInfo>()->setStackSizeSVE(ZPRStackSize,
4479+
PPRStackSize);
44804480
}
44814481

44824482
/// Attempts to scavenge a register from \p ScavengeableRegs given the used
@@ -4790,8 +4790,7 @@ void AArch64FrameLowering::processFunctionBeforeFrameFinalized(
47904790
assert(getStackGrowthDirection() == TargetFrameLowering::StackGrowsDown &&
47914791
"Upwards growing stack unsupported");
47924792

4793-
auto [ZPRStackSize, PPRStackSize] = assignSVEStackObjectOffsets(MF);
4794-
AFI->setStackSizeSVE(ZPRStackSize, PPRStackSize);
4793+
assignSVEStackObjectOffsets(MF);
47954794

47964795
// If this function isn't doing Win64-style C++ EH, we don't need to do
47974796
// anything.

llvm/lib/Target/AArch64/AArch64FrameLowering.h

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -20,8 +20,8 @@
2020
namespace llvm {
2121

2222
struct SVEStackSizes {
23-
int64_t ZPRStackSize{0};
24-
int64_t PPRStackSize{0};
23+
uint64_t ZPRStackSize{0};
24+
uint64_t PPRStackSize{0};
2525
};
2626

2727
class AArch64FrameLowering : public TargetFrameLowering {
@@ -153,7 +153,7 @@ class AArch64FrameLowering : public TargetFrameLowering {
153153
uint64_t StackBumpBytes) const;
154154

155155
SVEStackSizes estimateSVEStackObjectOffsets(MachineFunction &MF) const;
156-
SVEStackSizes assignSVEStackObjectOffsets(MachineFunction &MF) const;
156+
void assignSVEStackObjectOffsets(MachineFunction &MF) const;
157157
bool shouldCombineCSRLocalStackBumpInEpilogue(MachineBasicBlock &MBB,
158158
uint64_t StackBumpBytes) const;
159159
void emitCalleeSavedGPRLocations(MachineBasicBlock &MBB,

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