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Shao-Ce SUN
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[RISCV][CodeGen] Support Zdinx on RV32 codegen
This patch was split from D122918 . Co-Author: @stephenfan @liaolucy @realqhc Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D149743
1 parent ee1d5f6 commit 8b90f8e

32 files changed

+5903
-123
lines changed

‎llvm/docs/RISCVUsage.rst

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -100,7 +100,7 @@ on support follow.
100100
``Zbkc`` Supported
101101
``Zbkx`` Supported (`See note <#riscv-scalar-crypto-note1>`__)
102102
``Zbs`` Supported
103-
``Zdinx`` Assembly Support for RV32. Full support for RV64.
103+
``Zdinx`` Supported
104104
``Zfh`` Supported
105105
``Zfhmin`` Supported
106106
``Zfinx`` Supported

‎llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp

Lines changed: 91 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -50,6 +50,10 @@ class RISCVExpandPseudo : public MachineFunctionPass {
5050
bool expandVSetVL(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI);
5151
bool expandVMSET_VMCLR(MachineBasicBlock &MBB,
5252
MachineBasicBlock::iterator MBBI, unsigned Opcode);
53+
bool expandRV32ZdinxStore(MachineBasicBlock &MBB,
54+
MachineBasicBlock::iterator MBBI);
55+
bool expandRV32ZdinxLoad(MachineBasicBlock &MBB,
56+
MachineBasicBlock::iterator MBBI);
5357
#ifndef NDEBUG
5458
unsigned getInstSizeInBytes(const MachineFunction &MF) const {
5559
unsigned Size = 0;
@@ -101,6 +105,10 @@ bool RISCVExpandPseudo::expandMI(MachineBasicBlock &MBB,
101105
// expanded instructions for each pseudo is correct in the Size field of the
102106
// tablegen definition for the pseudo.
103107
switch (MBBI->getOpcode()) {
108+
case RISCV::PseudoRV32ZdinxSD:
109+
return expandRV32ZdinxStore(MBB, MBBI);
110+
case RISCV::PseudoRV32ZdinxLD:
111+
return expandRV32ZdinxLoad(MBB, MBBI);
104112
case RISCV::PseudoCCMOVGPR:
105113
case RISCV::PseudoCCADD:
106114
case RISCV::PseudoCCSUB:
@@ -251,6 +259,89 @@ bool RISCVExpandPseudo::expandVMSET_VMCLR(MachineBasicBlock &MBB,
251259
return true;
252260
}
253261

262+
// This function expands the PseudoRV32ZdinxSD for storing a double-precision
263+
// floating-point value into memory by generating an equivalent instruction
264+
// sequence for RV32.
265+
bool RISCVExpandPseudo::expandRV32ZdinxStore(MachineBasicBlock &MBB,
266+
MachineBasicBlock::iterator MBBI) {
267+
MachineFunction *MF = MBB.getParent();
268+
DebugLoc DL = MBBI->getDebugLoc();
269+
const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
270+
Register Lo = TRI->getSubReg(MBBI->getOperand(0).getReg(), RISCV::sub_32);
271+
Register Hi = TRI->getSubReg(MBBI->getOperand(0).getReg(), RISCV::sub_32_hi);
272+
BuildMI(MBB, MBBI, DL, TII->get(RISCV::SW))
273+
.addReg(Lo, getKillRegState(MBBI->getOperand(0).isKill()))
274+
.addReg(MBBI->getOperand(1).getReg())
275+
.add(MBBI->getOperand(2));
276+
if (MBBI->getOperand(2).isGlobal() || MBBI->getOperand(2).isCPI()) {
277+
// FIXME: Zdinx RV32 can not work on unaligned scalar memory.
278+
const auto &STI = MF->getSubtarget<RISCVSubtarget>();
279+
assert(!STI.enableUnalignedScalarMem());
280+
281+
assert(MBBI->getOperand(2).getOffset() % 8 == 0);
282+
MBBI->getOperand(2).setOffset(MBBI->getOperand(2).getOffset() + 4);
283+
BuildMI(MBB, MBBI, DL, TII->get(RISCV::SW))
284+
.addReg(Hi, getKillRegState(MBBI->getOperand(0).isKill()))
285+
.add(MBBI->getOperand(1))
286+
.add(MBBI->getOperand(2));
287+
} else {
288+
assert(isInt<12>(MBBI->getOperand(2).getImm() + 4));
289+
BuildMI(MBB, MBBI, DL, TII->get(RISCV::SW))
290+
.addReg(Hi, getKillRegState(MBBI->getOperand(0).isKill()))
291+
.add(MBBI->getOperand(1))
292+
.addImm(MBBI->getOperand(2).getImm() + 4);
293+
}
294+
MBBI->eraseFromParent();
295+
return true;
296+
}
297+
298+
// This function expands PseudoRV32ZdinxLoad for loading a double-precision
299+
// floating-point value from memory into an equivalent instruction sequence for
300+
// RV32.
301+
bool RISCVExpandPseudo::expandRV32ZdinxLoad(MachineBasicBlock &MBB,
302+
MachineBasicBlock::iterator MBBI) {
303+
MachineFunction *MF = MBB.getParent();
304+
DebugLoc DL = MBBI->getDebugLoc();
305+
const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
306+
Register Lo = TRI->getSubReg(MBBI->getOperand(0).getReg(), RISCV::sub_32);
307+
Register Hi = TRI->getSubReg(MBBI->getOperand(0).getReg(), RISCV::sub_32_hi);
308+
309+
// If the register of operand 1 is equal to the Lo register, then swap the
310+
// order of loading the Lo and Hi statements.
311+
bool IsOp1EqualToLo = Lo == MBBI->getOperand(1).getReg();
312+
// Order: Lo, Hi
313+
if (!IsOp1EqualToLo) {
314+
BuildMI(MBB, MBBI, DL, TII->get(RISCV::LW), Lo)
315+
.addReg(MBBI->getOperand(1).getReg())
316+
.add(MBBI->getOperand(2));
317+
}
318+
319+
if (MBBI->getOperand(2).isGlobal() || MBBI->getOperand(2).isCPI()) {
320+
auto Offset = MBBI->getOperand(2).getOffset();
321+
assert(MBBI->getOperand(2).getOffset() % 8 == 0);
322+
MBBI->getOperand(2).setOffset(Offset + 4);
323+
BuildMI(MBB, MBBI, DL, TII->get(RISCV::LW), Hi)
324+
.addReg(MBBI->getOperand(1).getReg())
325+
.add(MBBI->getOperand(2));
326+
MBBI->getOperand(2).setOffset(Offset);
327+
} else {
328+
assert(isInt<12>(MBBI->getOperand(2).getImm() + 4));
329+
BuildMI(MBB, MBBI, DL, TII->get(RISCV::LW), Hi)
330+
.addReg(MBBI->getOperand(1).getReg())
331+
.addImm(MBBI->getOperand(2).getImm() + 4);
332+
}
333+
334+
// Order: Hi, Lo
335+
if (IsOp1EqualToLo) {
336+
BuildMI(MBB, MBBI, DL, TII->get(RISCV::LW), Lo)
337+
.addReg(MBBI->getOperand(1).getReg())
338+
.add(MBBI->getOperand(2));
339+
}
340+
341+
MBBI->eraseFromParent();
342+
return true;
343+
}
344+
254345
class RISCVPreRAExpandPseudo : public MachineFunctionPass {
255346
public:
256347
const RISCVInstrInfo *TII;

‎llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp

Lines changed: 6 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -895,7 +895,7 @@ void RISCVDAGToDAGISel::Select(SDNode *Node) {
895895
if (Subtarget->is64Bit())
896896
Opc = HasZdinx ? RISCV::COPY : RISCV::FMV_D_X;
897897
else
898-
Opc = RISCV::FCVT_D_W;
898+
Opc = HasZdinx ? RISCV::FCVT_D_W_IN32X : RISCV::FCVT_D_W;
899899
break;
900900
}
901901

@@ -2309,7 +2309,7 @@ bool RISCVDAGToDAGISel::SelectAddrRegRegScale(SDValue Addr,
23092309
}
23102310

23112311
bool RISCVDAGToDAGISel::SelectAddrRegImm(SDValue Addr, SDValue &Base,
2312-
SDValue &Offset) {
2312+
SDValue &Offset, bool IsINX) {
23132313
if (SelectAddrFrameIndex(Addr, Base, Offset))
23142314
return true;
23152315

@@ -2322,9 +2322,10 @@ bool RISCVDAGToDAGISel::SelectAddrRegImm(SDValue Addr, SDValue &Base,
23222322
return true;
23232323
}
23242324

2325+
int64_t RV32ZdinxRange = IsINX ? 4 : 0;
23252326
if (CurDAG->isBaseWithConstantOffset(Addr)) {
23262327
int64_t CVal = cast<ConstantSDNode>(Addr.getOperand(1))->getSExtValue();
2327-
if (isInt<12>(CVal)) {
2328+
if (isInt<12>(CVal) && isInt<12>(CVal + RV32ZdinxRange)) {
23282329
Base = Addr.getOperand(0);
23292330
if (Base.getOpcode() == RISCVISD::ADD_LO) {
23302331
SDValue LoOperand = Base.getOperand(1);
@@ -2358,7 +2359,8 @@ bool RISCVDAGToDAGISel::SelectAddrRegImm(SDValue Addr, SDValue &Base,
23582359
// Handle ADD with large immediates.
23592360
if (Addr.getOpcode() == ISD::ADD && isa<ConstantSDNode>(Addr.getOperand(1))) {
23602361
int64_t CVal = cast<ConstantSDNode>(Addr.getOperand(1))->getSExtValue();
2361-
assert(!isInt<12>(CVal) && "simm12 not already handled?");
2362+
assert(!(isInt<12>(CVal) && isInt<12>(CVal + RV32ZdinxRange)) &&
2363+
"simm12 not already handled?");
23622364

23632365
// Handle immediates in the range [-4096,-2049] or [2048, 4094]. We can use
23642366
// an ADDI for part of the offset and fold the rest into the load/store.

‎llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h

Lines changed: 5 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -48,7 +48,11 @@ class RISCVDAGToDAGISel : public SelectionDAGISel {
4848

4949
bool SelectAddrFrameIndex(SDValue Addr, SDValue &Base, SDValue &Offset);
5050
bool SelectFrameAddrRegImm(SDValue Addr, SDValue &Base, SDValue &Offset);
51-
bool SelectAddrRegImm(SDValue Addr, SDValue &Base, SDValue &Offset);
51+
bool SelectAddrRegImm(SDValue Addr, SDValue &Base, SDValue &Offset,
52+
bool IsINX = false);
53+
bool SelectAddrRegImmINX(SDValue Addr, SDValue &Base, SDValue &Offset) {
54+
return SelectAddrRegImm(Addr, Base, Offset, true);
55+
}
5256

5357
bool SelectAddrRegRegScale(SDValue Addr, unsigned MaxShiftAmount,
5458
SDValue &Base, SDValue &Index, SDValue &Scale);

‎llvm/lib/Target/RISCV/RISCVISelLowering.cpp

Lines changed: 26 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -127,6 +127,8 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
127127
if (Subtarget.hasStdExtZdinx()) {
128128
if (Subtarget.is64Bit())
129129
addRegisterClass(MVT::f64, &RISCV::GPRF64RegClass);
130+
else
131+
addRegisterClass(MVT::f64, &RISCV::GPRPF64RegClass);
130132
}
131133

132134
static const MVT::SimpleValueType BoolVecVTs[] = {
@@ -12842,7 +12844,9 @@ static MachineBasicBlock *emitReadCycleWidePseudo(MachineInstr &MI,
1284212844
static MachineBasicBlock *emitSplitF64Pseudo(MachineInstr &MI,
1284312845
MachineBasicBlock *BB,
1284412846
const RISCVSubtarget &Subtarget) {
12845-
assert(MI.getOpcode() == RISCV::SplitF64Pseudo && "Unexpected instruction");
12847+
assert((MI.getOpcode() == RISCV::SplitF64Pseudo ||
12848+
MI.getOpcode() == RISCV::SplitF64Pseudo_INX) &&
12849+
"Unexpected instruction");
1284612850

1284712851
MachineFunction &MF = *BB->getParent();
1284812852
DebugLoc DL = MI.getDebugLoc();
@@ -12852,7 +12856,9 @@ static MachineBasicBlock *emitSplitF64Pseudo(MachineInstr &MI,
1285212856
Register HiReg = MI.getOperand(1).getReg();
1285312857
Register SrcReg = MI.getOperand(2).getReg();
1285412858

12855-
const TargetRegisterClass *SrcRC = &RISCV::FPR64RegClass;
12859+
const TargetRegisterClass *SrcRC = MI.getOpcode() == RISCV::SplitF64Pseudo_INX
12860+
? &RISCV::GPRPF64RegClass
12861+
: &RISCV::FPR64RegClass;
1285612862
int FI = MF.getInfo<RISCVMachineFunctionInfo>()->getMoveF64FrameIndex(MF);
1285712863

1285812864
TII.storeRegToStackSlot(*BB, MI, SrcReg, MI.getOperand(2).isKill(), FI, SrcRC,
@@ -12877,7 +12883,8 @@ static MachineBasicBlock *emitSplitF64Pseudo(MachineInstr &MI,
1287712883
static MachineBasicBlock *emitBuildPairF64Pseudo(MachineInstr &MI,
1287812884
MachineBasicBlock *BB,
1287912885
const RISCVSubtarget &Subtarget) {
12880-
assert(MI.getOpcode() == RISCV::BuildPairF64Pseudo &&
12886+
assert((MI.getOpcode() == RISCV::BuildPairF64Pseudo ||
12887+
MI.getOpcode() == RISCV::BuildPairF64Pseudo_INX) &&
1288112888
"Unexpected instruction");
1288212889

1288312890
MachineFunction &MF = *BB->getParent();
@@ -12888,7 +12895,9 @@ static MachineBasicBlock *emitBuildPairF64Pseudo(MachineInstr &MI,
1288812895
Register LoReg = MI.getOperand(1).getReg();
1288912896
Register HiReg = MI.getOperand(2).getReg();
1289012897

12891-
const TargetRegisterClass *DstRC = &RISCV::FPR64RegClass;
12898+
const TargetRegisterClass *DstRC =
12899+
MI.getOpcode() == RISCV::BuildPairF64Pseudo_INX ? &RISCV::GPRPF64RegClass
12900+
: &RISCV::FPR64RegClass;
1289212901
int FI = MF.getInfo<RISCVMachineFunctionInfo>()->getMoveF64FrameIndex(MF);
1289312902

1289412903
MachinePointerInfo MPI = MachinePointerInfo::getFixedStack(MF, FI);
@@ -12922,6 +12931,7 @@ static bool isSelectPseudo(MachineInstr &MI) {
1292212931
case RISCV::Select_FPR32INX_Using_CC_GPR:
1292312932
case RISCV::Select_FPR64_Using_CC_GPR:
1292412933
case RISCV::Select_FPR64INX_Using_CC_GPR:
12934+
case RISCV::Select_FPR64IN32X_Using_CC_GPR:
1292512935
return true;
1292612936
}
1292712937
}
@@ -13432,10 +13442,13 @@ RISCVTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
1343213442
case RISCV::Select_FPR32INX_Using_CC_GPR:
1343313443
case RISCV::Select_FPR64_Using_CC_GPR:
1343413444
case RISCV::Select_FPR64INX_Using_CC_GPR:
13445+
case RISCV::Select_FPR64IN32X_Using_CC_GPR:
1343513446
return emitSelectPseudo(MI, BB, Subtarget);
1343613447
case RISCV::BuildPairF64Pseudo:
13448+
case RISCV::BuildPairF64Pseudo_INX:
1343713449
return emitBuildPairF64Pseudo(MI, BB, Subtarget);
1343813450
case RISCV::SplitF64Pseudo:
13451+
case RISCV::SplitF64Pseudo_INX:
1343913452
return emitSplitF64Pseudo(MI, BB, Subtarget);
1344013453
case RISCV::PseudoQuietFLE_H:
1344113454
return emitQuietFCMP(MI, BB, RISCV::FLE_H, RISCV::FEQ_H, Subtarget);
@@ -13457,10 +13470,16 @@ RISCVTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
1345713470
return emitQuietFCMP(MI, BB, RISCV::FLE_D, RISCV::FEQ_D, Subtarget);
1345813471
case RISCV::PseudoQuietFLE_D_INX:
1345913472
return emitQuietFCMP(MI, BB, RISCV::FLE_D_INX, RISCV::FEQ_D_INX, Subtarget);
13473+
case RISCV::PseudoQuietFLE_D_IN32X:
13474+
return emitQuietFCMP(MI, BB, RISCV::FLE_D_IN32X, RISCV::FEQ_D_IN32X,
13475+
Subtarget);
1346013476
case RISCV::PseudoQuietFLT_D:
1346113477
return emitQuietFCMP(MI, BB, RISCV::FLT_D, RISCV::FEQ_D, Subtarget);
1346213478
case RISCV::PseudoQuietFLT_D_INX:
1346313479
return emitQuietFCMP(MI, BB, RISCV::FLT_D_INX, RISCV::FEQ_D_INX, Subtarget);
13480+
case RISCV::PseudoQuietFLT_D_IN32X:
13481+
return emitQuietFCMP(MI, BB, RISCV::FLT_D_IN32X, RISCV::FEQ_D_IN32X,
13482+
Subtarget);
1346413483

1346513484
// =========================================================================
1346613485
// VFCVT
@@ -13646,6 +13665,7 @@ RISCVTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
1364613665
case RISCV::PseudoFROUND_S_INX:
1364713666
case RISCV::PseudoFROUND_D:
1364813667
case RISCV::PseudoFROUND_D_INX:
13668+
case RISCV::PseudoFROUND_D_IN32X:
1364913669
return emitFROUND(MI, BB, Subtarget);
1365013670
}
1365113671
}
@@ -15507,7 +15527,8 @@ RISCVTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
1550715527
// Subtarget into account.
1550815528
if (Res.second == &RISCV::GPRF16RegClass ||
1550915529
Res.second == &RISCV::GPRF32RegClass ||
15510-
Res.second == &RISCV::GPRF64RegClass)
15530+
Res.second == &RISCV::GPRF64RegClass ||
15531+
Res.second == &RISCV::GPRPF64RegClass)
1551115532
return std::make_pair(Res.first, &RISCV::GPRRegClass);
1551215533

1551315534
return Res;

‎llvm/lib/Target/RISCV/RISCVInstrInfo.cpp

Lines changed: 17 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -297,6 +297,13 @@ void RISCVInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
297297
MachineBasicBlock::iterator MBBI,
298298
const DebugLoc &DL, MCRegister DstReg,
299299
MCRegister SrcReg, bool KillSrc) const {
300+
const TargetRegisterInfo *TRI = STI.getRegisterInfo();
301+
302+
if (RISCV::GPRPF64RegClass.contains(DstReg))
303+
DstReg = TRI->getSubReg(DstReg, RISCV::sub_32);
304+
if (RISCV::GPRPF64RegClass.contains(SrcReg))
305+
SrcReg = TRI->getSubReg(SrcReg, RISCV::sub_32);
306+
300307
if (RISCV::GPRRegClass.contains(DstReg, SrcReg)) {
301308
BuildMI(MBB, MBBI, DL, get(RISCV::ADDI), DstReg)
302309
.addReg(SrcReg, getKillRegState(KillSrc))
@@ -307,10 +314,9 @@ void RISCVInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
307314
// Handle copy from csr
308315
if (RISCV::VCSRRegClass.contains(SrcReg) &&
309316
RISCV::GPRRegClass.contains(DstReg)) {
310-
const TargetRegisterInfo &TRI = *STI.getRegisterInfo();
311317
BuildMI(MBB, MBBI, DL, get(RISCV::CSRRS), DstReg)
312-
.addImm(RISCVSysReg::lookupSysRegByName(TRI.getName(SrcReg))->Encoding)
313-
.addReg(RISCV::X0);
318+
.addImm(RISCVSysReg::lookupSysRegByName(TRI->getName(SrcReg))->Encoding)
319+
.addReg(RISCV::X0);
314320
return;
315321
}
316322

@@ -323,7 +329,6 @@ void RISCVInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
323329
if (RISCV::FPR16RegClass.contains(DstReg, SrcReg)) {
324330
if (!STI.hasStdExtZfh() && STI.hasStdExtZfhmin()) {
325331
// Zfhmin subset doesn't have FSGNJ_H, replaces FSGNJ_H with FSGNJ_S.
326-
const TargetRegisterInfo *TRI = STI.getRegisterInfo();
327332
DstReg = TRI->getMatchingSuperReg(DstReg, RISCV::sub_16,
328333
&RISCV::FPR32RegClass);
329334
SrcReg = TRI->getMatchingSuperReg(SrcReg, RISCV::sub_16,
@@ -460,8 +465,6 @@ void RISCVInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
460465
MIB.addReg(RISCV::VTYPE, RegState::Implicit);
461466
}
462467
} else {
463-
const TargetRegisterInfo *TRI = STI.getRegisterInfo();
464-
465468
int I = 0, End = NF, Incr = 1;
466469
unsigned SrcEncoding = TRI->getEncodingValue(SrcReg);
467470
unsigned DstEncoding = TRI->getEncodingValue(DstReg);
@@ -518,6 +521,9 @@ void RISCVInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
518521
Opcode = TRI->getRegSizeInBits(RISCV::GPRRegClass) == 32 ?
519522
RISCV::SW : RISCV::SD;
520523
IsScalableVector = false;
524+
} else if (RISCV::GPRPF64RegClass.hasSubClassEq(RC)) {
525+
Opcode = RISCV::PseudoRV32ZdinxSD;
526+
IsScalableVector = false;
521527
} else if (RISCV::FPR16RegClass.hasSubClassEq(RC)) {
522528
Opcode = RISCV::FSH;
523529
IsScalableVector = false;
@@ -602,6 +608,9 @@ void RISCVInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
602608
Opcode = TRI->getRegSizeInBits(RISCV::GPRRegClass) == 32 ?
603609
RISCV::LW : RISCV::LD;
604610
IsScalableVector = false;
611+
} else if (RISCV::GPRPF64RegClass.hasSubClassEq(RC)) {
612+
Opcode = RISCV::PseudoRV32ZdinxLD;
613+
IsScalableVector = false;
605614
} else if (RISCV::FPR16RegClass.hasSubClassEq(RC)) {
606615
Opcode = RISCV::FLH;
607616
IsScalableVector = false;
@@ -1272,6 +1281,7 @@ bool RISCVInstrInfo::isAsCheapAsAMove(const MachineInstr &MI) const {
12721281
case RISCV::FSGNJ_S:
12731282
case RISCV::FSGNJ_H:
12741283
case RISCV::FSGNJ_D_INX:
1284+
case RISCV::FSGNJ_D_IN32X:
12751285
case RISCV::FSGNJ_S_INX:
12761286
case RISCV::FSGNJ_H_INX:
12771287
// The canonical floating-point move is fsgnj rd, rs, rs.
@@ -1304,6 +1314,7 @@ RISCVInstrInfo::isCopyInstrImpl(const MachineInstr &MI) const {
13041314
case RISCV::FSGNJ_S:
13051315
case RISCV::FSGNJ_H:
13061316
case RISCV::FSGNJ_D_INX:
1317+
case RISCV::FSGNJ_D_IN32X:
13071318
case RISCV::FSGNJ_S_INX:
13081319
case RISCV::FSGNJ_H_INX:
13091320
// The canonical floating-point move is fsgnj rd, rs, rs.

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