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[AArch64] Add support for -mcpu=gb10. (#146515)
This patch adds support for -mcpu=gb10 (NVIDIA GB10). This is a big.LITTLE cluster of Cortex-X925 and Cortex-A725 cores. The appropriate MIDR numbers are added to detect them in -mcpu=native. We did not add an -mcpu=cortex-x925.cortex-a725 option because GB10 does include the crypto instructions which we want on by default, and the current convention is to not enable such extensions for Arm Cortex cores in -mcpu where they are optional in the IP. Relevant GCC patch: https://gcc.gnu.org/pipermail/gcc-patches/2025-June/687005.html
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‎clang/test/Driver/print-enabled-extensions/aarch64-gb10.c

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// REQUIRES: aarch64-registered-target
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// RUN: %clang --target=aarch64 --print-enabled-extensions -mcpu=gb10 | FileCheck --strict-whitespace --implicit-check-not=FEAT_ %s
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// CHECK: Extensions enabled for the given AArch64 target
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// CHECK-EMPTY:
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// CHECK-NEXT: Architecture Feature(s) Description
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// CHECK-NEXT: FEAT_AES, FEAT_PMULL Enable AES support
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// CHECK-NEXT: FEAT_AMUv1 Enable Armv8.4-A Activity Monitors extension
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// CHECK-NEXT: FEAT_AMUv1p1 Enable Armv8.6-A Activity Monitors Virtualization support
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// CHECK-NEXT: FEAT_AdvSIMD Enable Advanced SIMD instructions
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// CHECK-NEXT: FEAT_BF16 Enable BFloat16 Extension
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// CHECK-NEXT: FEAT_BTI Enable Branch Target Identification
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// CHECK-NEXT: FEAT_CCIDX Enable Armv8.3-A Extend of the CCSIDR number of sets
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// CHECK-NEXT: FEAT_CRC32 Enable Armv8.0-A CRC-32 checksum instructions
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// CHECK-NEXT: FEAT_CSV2_2 Enable architectural speculation restriction
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// CHECK-NEXT: FEAT_DIT Enable Armv8.4-A Data Independent Timing instructions
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// CHECK-NEXT: FEAT_DPB Enable Armv8.2-A data Cache Clean to Point of Persistence
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// CHECK-NEXT: FEAT_DPB2 Enable Armv8.5-A Cache Clean to Point of Deep Persistence
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// CHECK-NEXT: FEAT_DotProd Enable dot product support
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// CHECK-NEXT: FEAT_ECV Enable enhanced counter virtualization extension
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// CHECK-NEXT: FEAT_ETE Enable Embedded Trace Extension
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// CHECK-NEXT: FEAT_FCMA Enable Armv8.3-A Floating-point complex number support
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// CHECK-NEXT: FEAT_FGT Enable fine grained virtualization traps extension
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// CHECK-NEXT: FEAT_FHM Enable FP16 FML instructions
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// CHECK-NEXT: FEAT_FP Enable Armv8.0-A Floating Point Extensions
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// CHECK-NEXT: FEAT_FP16 Enable half-precision floating-point data processing
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// CHECK-NEXT: FEAT_FPAC Enable Armv8.3-A Pointer Authentication Faulting enhancement
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// CHECK-NEXT: FEAT_FRINTTS Enable FRInt[32|64][Z|X] instructions that round a floating-point number to an integer (in FP format) forcing it to fit into a 32- or 64-bit int
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// CHECK-NEXT: FEAT_FlagM Enable Armv8.4-A Flag Manipulation instructions
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// CHECK-NEXT: FEAT_FlagM2 Enable alternative NZCV format for floating point comparisons
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// CHECK-NEXT: FEAT_HCX Enable Armv8.7-A HCRX_EL2 system register
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// CHECK-NEXT: FEAT_I8MM Enable Matrix Multiply Int8 Extension
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// CHECK-NEXT: FEAT_JSCVT Enable Armv8.3-A JavaScript FP conversion instructions
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// CHECK-NEXT: FEAT_LOR Enable Armv8.1-A Limited Ordering Regions extension
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// CHECK-NEXT: FEAT_LRCPC Enable support for RCPC extension
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// CHECK-NEXT: FEAT_LRCPC2 Enable Armv8.4-A RCPC instructions with Immediate Offsets
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// CHECK-NEXT: FEAT_LSE Enable Armv8.1-A Large System Extension (LSE) atomic instructions
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// CHECK-NEXT: FEAT_LSE2 Enable Armv8.4-A Large System Extension 2 (LSE2) atomicity rules
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// CHECK-NEXT: FEAT_MPAM Enable Armv8.4-A Memory system Partitioning and Monitoring extension
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// CHECK-NEXT: FEAT_MTE, FEAT_MTE2 Enable Memory Tagging Extension
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// CHECK-NEXT: FEAT_NV, FEAT_NV2 Enable Armv8.4-A Nested Virtualization Enchancement
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// CHECK-NEXT: FEAT_PAN Enable Armv8.1-A Privileged Access-Never extension
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// CHECK-NEXT: FEAT_PAN2 Enable Armv8.2-A PAN s1e1R and s1e1W Variants
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// CHECK-NEXT: FEAT_PAuth Enable Armv8.3-A Pointer Authentication extension
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// CHECK-NEXT: FEAT_PMUv3 Enable Armv8.0-A PMUv3 Performance Monitors extension
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// CHECK-NEXT: FEAT_RAS, FEAT_RASv1p1 Enable Armv8.0-A Reliability, Availability and Serviceability Extensions
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// CHECK-NEXT: FEAT_RDM Enable Armv8.1-A Rounding Double Multiply Add/Subtract instructions
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// CHECK-NEXT: FEAT_SB Enable Armv8.5-A Speculation Barrier
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// CHECK-NEXT: FEAT_SEL2 Enable Armv8.4-A Secure Exception Level 2 extension
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// CHECK-NEXT: FEAT_SHA1, FEAT_SHA256 Enable SHA1 and SHA256 support
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// CHECK-NEXT: FEAT_SHA3, FEAT_SHA512 Enable SHA512 and SHA3 support
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// CHECK-NEXT: FEAT_SM4, FEAT_SM3 Enable SM3 and SM4 support
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// CHECK-NEXT: FEAT_SPE Enable Statistical Profiling extension
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// CHECK-NEXT: FEAT_SPECRES Enable Armv8.5-A execution and data prediction invalidation instructions
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// CHECK-NEXT: FEAT_SPEv1p2 Enable extra register in the Statistical Profiling Extension
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// CHECK-NEXT: FEAT_SSBS, FEAT_SSBS2 Enable Speculative Store Bypass Safe bit
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// CHECK-NEXT: FEAT_SVE Enable Scalable Vector Extension (SVE) instructions
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// CHECK-NEXT: FEAT_SVE2 Enable Scalable Vector Extension 2 (SVE2) instructions
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// CHECK-NEXT: FEAT_SVE_AES, FEAT_SVE_PMULL128 Enable SVE AES and quadword SVE polynomial multiply instructions
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// CHECK-NEXT: FEAT_SVE_BitPerm Enable bit permutation SVE2 instructions
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// CHECK-NEXT: FEAT_SVE_SHA3 Enable SVE SHA3 instructions
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// CHECK-NEXT: FEAT_SVE_SM4 Enable SM4 SVE2 instructions
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// CHECK-NEXT: FEAT_TLBIOS, FEAT_TLBIRANGE Enable Armv8.4-A TLB Range and Maintenance instructions
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// CHECK-NEXT: FEAT_TRBE Enable Trace Buffer Extension
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// CHECK-NEXT: FEAT_TRF Enable Armv8.4-A Trace extension
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// CHECK-NEXT: FEAT_UAO Enable Armv8.2-A UAO PState
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// CHECK-NEXT: FEAT_VHE Enable Armv8.1-A Virtual Host extension
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// CHECK-NEXT: FEAT_WFxT Enable Armv8.7-A WFET and WFIT instruction
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// CHECK-NEXT: FEAT_XS Enable Armv8.7-A limited-TLB-maintenance instruction

‎clang/test/Misc/target-invalid-cpu-note/aarch64.c

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// CHECK-SAME: {{^}}, exynos-m5
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// CHECK-SAME: {{^}}, falkor
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// CHECK-SAME: {{^}}, fujitsu-monaka
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// CHECK-SAME: {{^}}, gb10
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// CHECK-SAME: {{^}}, generic
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// CHECK-SAME: {{^}}, grace
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// CHECK-SAME: {{^}}, kryo

‎llvm/lib/Target/AArch64/AArch64Processors.td

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@@ -1117,6 +1117,7 @@ def ProcessorFeatures {
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FeatureDotProd, FeatureFPARMv8, FeatureMatMulInt8,
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FeatureSSBS, FeatureCCIDX,
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FeatureJS, FeatureLSE, FeatureRAS, FeatureRCPC, FeatureRDM];
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list<SubtargetFeature> GB10 = !listconcat(X925, [FeatureSVEAES, FeatureSVESHA3, FeatureSVE2SM4]);
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list<SubtargetFeature> Grace = !listconcat(NeoverseV2, [FeatureSVE2SM4, FeatureSVEAES, FeatureSVESHA3]);
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// ETE and TRBE are future architecture extensions. We temporarily enable them
@@ -1203,6 +1204,8 @@ def : ProcessorModel<"cortex-x4", NeoverseV2Model, ProcessorFeatures.X4,
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[TuneX4]>;
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def : ProcessorModel<"cortex-x925", NeoverseV2Model, ProcessorFeatures.X925,
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[TuneX925]>;
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def : ProcessorModel<"gb10", NeoverseV2Model, ProcessorFeatures.GB10,
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[TuneX925]>;
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def : ProcessorModel<"grace", NeoverseV2Model, ProcessorFeatures.Grace,
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[TuneNeoverseV2]>;
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def : ProcessorModel<"neoverse-e1", CortexA53Model,

‎llvm/lib/TargetParser/Host.cpp

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@@ -176,25 +176,43 @@ StringRef sys::detail::getHostCPUNameForARM(StringRef ProcCpuinfoContent) {
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SmallVector<StringRef, 32> Lines;
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ProcCpuinfoContent.split(Lines, '\n');
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// Look for the CPU implementer line.
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// Look for the CPU implementer and hardware lines, and store the CPU part
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// numbers found.
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StringRef Implementer;
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StringRef Hardware;
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StringRef Part;
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SmallVector<StringRef, 32> Parts;
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for (StringRef Line : Lines) {
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if (Line.consume_front("CPU implementer"))
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Implementer = Line.ltrim("\t :");
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else if (Line.consume_front("Hardware"))
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Hardware = Line.ltrim("\t :");
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else if (Line.consume_front("CPU part"))
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Part = Line.ltrim("\t :");
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Parts.emplace_back(Line.ltrim("\t :"));
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}
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// Last `Part' seen, in case we don't analyse all `Parts' parsed.
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StringRef Part = Parts.empty() ? StringRef() : Parts.back();
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// Remove duplicate `Parts'.
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llvm::sort(Parts);
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Parts.erase(llvm::unique(Parts), Parts.end());
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auto MatchBigLittle = [](auto const &Parts, StringRef Big, StringRef Little) {
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if (Parts.size() == 2)
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return (Parts[0] == Big && Parts[1] == Little) ||
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(Parts[1] == Big && Parts[0] == Little);
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return false;
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};
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if (Implementer == "0x41") { // ARM Ltd.
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// MSM8992/8994 may give cpu part for the core that the kernel is running on,
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// which is undeterministic and wrong. Always return cortex-a53 for these SoC.
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if (Hardware.ends_with("MSM8994") || Hardware.ends_with("MSM8996"))
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return "cortex-a53";
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// Detect big.LITTLE systems.
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if (MatchBigLittle(Parts, "0xd85", "0xd87"))
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return "cortex-x925";
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// The CPU part is a 3 digit hexadecimal number with a 0x prefix. The
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// values correspond to the "Part number" in the CP15/c0 register. The

‎llvm/unittests/TargetParser/Host.cpp

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@@ -122,6 +122,14 @@ TEST(getLinuxHostCPUName, AArch64) {
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EXPECT_EQ(sys::detail::getHostCPUNameForARM("CPU implementer : 0x41\n"
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"CPU part : 0xd48"),
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"cortex-x2");
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EXPECT_EQ(sys::detail::getHostCPUNameForARM("CPU implementer : 0x41\n"
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"CPU part : 0xd85\n"
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"CPU part : 0xd87"),
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"cortex-x925");
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EXPECT_EQ(sys::detail::getHostCPUNameForARM("CPU implementer : 0x41\n"
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"CPU part : 0xd87\n"
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"CPU part : 0xd85"),
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"cortex-x925");
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EXPECT_EQ(sys::detail::getHostCPUNameForARM("CPU implementer : 0x51\n"
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"CPU part : 0xc00"),
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"falkor");

‎llvm/unittests/TargetParser/TargetParserTest.cpp

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@@ -1164,6 +1164,7 @@ INSTANTIATE_TEST_SUITE_P(
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AArch64CPUTestParams("a64fx", "armv8.2-a"),
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AArch64CPUTestParams("fujitsu-monaka", "armv9.3-a"),
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AArch64CPUTestParams("carmel", "armv8.2-a"),
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AArch64CPUTestParams("gb10", "armv9.2-a"),
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AArch64CPUTestParams("grace", "armv9-a"),
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AArch64CPUTestParams("olympus", "armv9.2-a"),
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AArch64CPUTestParams("saphira", "armv8.4-a"),
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AArch64CPUAliasTestParams::PrintToStringParamName);
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// Note: number of CPUs includes aliases.
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static constexpr unsigned NumAArch64CPUArchs = 90;
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static constexpr unsigned NumAArch64CPUArchs = 91;
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TEST(TargetParserTest, testAArch64CPUArchList) {
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SmallVector<StringRef, NumAArch64CPUArchs> List;

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