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[Hexagon]Handle bitcast of i32/v2i16/v4i8 -> v32i1 when Hvx is enabled
Change-Id: I1f3c4783424a2c068f207a7680f85ef95c70f573
1 parent 18991f4 commit 8152d6f

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‎llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp

Lines changed: 24 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -117,6 +117,8 @@ HexagonTargetLowering::initializeHVXLowering() {
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setOperationAction(ISD::VECTOR_SHUFFLE, ByteW, Legal);
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setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
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if (Subtarget.useHVX128BOps())
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setOperationAction(ISD::BITCAST, MVT::v32i1, Custom);
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if (Subtarget.useHVX128BOps() && Subtarget.useHVXV68Ops() &&
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Subtarget.useHVXFloatingPoint()) {
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@@ -2001,6 +2003,28 @@ HexagonTargetLowering::LowerHvxBitcast(SDValue Op, SelectionDAG &DAG) const {
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20022004
return DAG.getNode(ISD::BUILD_PAIR, dl, ResTy, Combines);
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}
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// Handle bitcast from i32, v2i16, and v4i8 to v32i1.
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// Splat the input into a 32-element i32 vector, then AND each element
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// with a unique bitmask to isolate individual bits.
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if (ResTy == MVT::v32i1 &&
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(ValTy == MVT::i32 || ValTy == MVT::v2i16 || ValTy == MVT::v4i8) &&
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Subtarget.useHVX128BOps()) {
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SDValue Val32 = Val;
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if (ValTy == MVT::v2i16 || ValTy == MVT::v4i8)
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Val32 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Val);
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MVT VecTy = MVT::getVectorVT(MVT::i32, 32);
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SDValue Splat = DAG.getNode(ISD::SPLAT_VECTOR, dl, VecTy, Val32);
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SmallVector<SDValue, 32> Mask;
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for (unsigned i = 0; i < 32; ++i)
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Mask.push_back(DAG.getConstant(1u << i, dl, MVT::i32));
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SDValue MaskVec = DAG.getBuildVector(VecTy, dl, Mask);
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SDValue Anded = DAG.getNode(ISD::AND, dl, VecTy, Splat, MaskVec);
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return DAG.getNode(HexagonISD::V2Q, dl, ResTy, Anded);
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}
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20042028
if (isHvxBoolTy(ResTy) && ValTy.isScalarInteger()) {
20052029
// Handle bitcast from i128 -> v128i1 and i64 -> v64i1.
20062030
unsigned BitWidth = ValTy.getSizeInBits();

‎llvm/test/CodeGen/Hexagon/bitcast-i32-to-v32i1.ll

Lines changed: 69 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,69 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc --mtriple=hexagon -mattr=+hvxv79,+hvx-length128b < %s | FileCheck %s
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define void @bitcast_i32_to_v32i1(ptr %in, ptr %out) {
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; CHECK-LABEL: bitcast_i32_to_v32i1:
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; CHECK: .cfi_startproc
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; CHECK-NEXT: // %bb.0: // %entry
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; CHECK-NEXT: {
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; CHECK-NEXT: r3:2 = combine(#-1,##.LCPI0_0)
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; CHECK-NEXT: allocframe(r29,#128):raw
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; CHECK-NEXT: }
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; CHECK-NEXT: .cfi_def_cfa r30, 8
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; CHECK-NEXT: .cfi_offset r31, -4
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; CHECK-NEXT: .cfi_offset r30, -8
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; CHECK-NEXT: {
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; CHECK-NEXT: r29 = and(r29,#-128)
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; CHECK-NEXT: r0 = memw(r0+#0)
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; CHECK-NEXT: v1 = vmem(r2+#0)
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: v0 = vsplat(r0)
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; CHECK-NEXT: r5 = add(r29,#0)
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: v0 = vand(v0,v1)
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: q0 = vand(v0,r3)
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: v0 = vand(q0,r3)
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; CHECK-NEXT: vmem(r5+#0) = v0.new
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: r4 = memw(r5+#0)
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; CHECK-NEXT: r0 = memw(r5+#4)
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: r2 = and(r4,#255)
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; CHECK-NEXT: r0 = and(r0,#255)
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: p1 = cmp.gtu(r2,#0)
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; CHECK-NEXT: p0 = cmp.gtu(r0,#0)
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: r0 = mux(p1,#1,#0)
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; CHECK-NEXT: r2 = mux(p0,#1,#0)
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; CHECK-NEXT: memb(r1+#0) = r0.new
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: memb(r1+#1) = r2
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: r31:30 = dealloc_return(r30):raw
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; CHECK-NEXT: }
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entry:
58+
%load = load i32, ptr %in, align 4
59+
%bitcast = bitcast i32 %load to <32 x i1>
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%e0 = extractelement <32 x i1> %bitcast, i32 0
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%e1 = extractelement <32 x i1> %bitcast, i32 1
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%z0 = zext i1 %e0 to i8
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%z1 = zext i1 %e1 to i8
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%ptr0 = getelementptr i8, ptr %out, i32 0
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%ptr1 = getelementptr i8, ptr %out, i32 1
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store i8 %z0, ptr %ptr0, align 1
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store i8 %z1, ptr %ptr1, align 1
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ret void
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}

‎llvm/test/CodeGen/Hexagon/bitcast-v2i16-to-v32i1.ll

Lines changed: 47 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,47 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc --mtriple=hexagon -mattr=+hvxv79,+hvx-length128b < %s | FileCheck %s
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define void @bitcast_v2i16_to_v32i1(ptr %in, ptr %out) {
5+
; CHECK-LABEL: bitcast_v2i16_to_v32i1:
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; CHECK: .cfi_startproc
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; CHECK-NEXT: // %bb.0: // %entry
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; CHECK-NEXT: {
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; CHECK-NEXT: r3:2 = combine(#-1,##.LCPI0_0)
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; CHECK-NEXT: r0 = memw(r0+#0)
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: v0 = vsplat(r0)
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; CHECK-NEXT: r2 = #0
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; CHECK-NEXT: v1 = vmem(r2+#0)
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: v0 = vand(v0,v1)
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: q0 = vand(v0,r3)
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: v0 = vand(q0,r3)
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: r0 = vextract(v0,r2)
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: r0 = and(r0,#255)
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: p0 = cmp.gtu(r0,#0)
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; CHECK-NEXT: }
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; CHECK-NEXT: {
36+
; CHECK-NEXT: r0 = mux(p0,#1,#0)
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; CHECK-NEXT: jumpr r31
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; CHECK-NEXT: memb(r1+#0) = r0.new
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; CHECK-NEXT: }
40+
entry:
41+
%load = load <2 x i16>, ptr %in, align 4
42+
%bitcast = bitcast <2 x i16> %load to <32 x i1>
43+
%extract = extractelement <32 x i1> %bitcast, i32 0
44+
%zext = zext i1 %extract to i8
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store i8 %zext, ptr %out, align 1
46+
ret void
47+
}

‎llvm/test/CodeGen/Hexagon/bitcast-v4i8-to-v32i1.ll

Lines changed: 47 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,47 @@
1+
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
2+
; RUN: llc --mtriple=hexagon -mattr=+hvxv79,+hvx-length128b < %s | FileCheck %s
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4+
define void @bitcast_v4i8_to_v32i1(ptr %in, ptr %out) {
5+
; CHECK-LABEL: bitcast_v4i8_to_v32i1:
6+
; CHECK: .cfi_startproc
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; CHECK-NEXT: // %bb.0: // %entry
8+
; CHECK-NEXT: {
9+
; CHECK-NEXT: r3:2 = combine(#-1,##.LCPI0_0)
10+
; CHECK-NEXT: r0 = memw(r0+#0)
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: v0 = vsplat(r0)
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; CHECK-NEXT: r2 = #0
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; CHECK-NEXT: v1 = vmem(r2+#0)
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: v0 = vand(v0,v1)
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: q0 = vand(v0,r3)
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; CHECK-NEXT: }
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; CHECK-NEXT: {
24+
; CHECK-NEXT: v0 = vand(q0,r3)
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: r0 = vextract(v0,r2)
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; CHECK-NEXT: }
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; CHECK-NEXT: {
30+
; CHECK-NEXT: r0 = and(r0,#255)
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: p0 = cmp.gtu(r0,#0)
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: r0 = mux(p0,#1,#0)
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; CHECK-NEXT: jumpr r31
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; CHECK-NEXT: memb(r1+#0) = r0.new
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; CHECK-NEXT: }
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entry:
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%load = load <4 x i8>, ptr %in, align 4
42+
%bitcast = bitcast <4 x i8> %load to <32 x i1>
43+
%extract = extractelement <32 x i1> %bitcast, i32 0
44+
%zext = zext i1 %extract to i8
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store i8 %zext, ptr %out, align 1
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ret void
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}

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