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[Codegen] Add a separate stack ID for scalable predicates
This splits out "ScalablePredVector" from the "ScalableVector" StackID this is primarily to allow easy differentiation between vectors and predicates (without inspecting instructions). This new stack ID is not used in many places yet, but will be used in a later patch to mark stack slots that are known to contain predicates.
1 parent 95ea436 commit 813787f

14 files changed

+66
-52
lines changed

‎llvm/include/llvm/CodeGen/MIRYamlMapping.h

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -378,6 +378,7 @@ struct ScalarEnumerationTraits<TargetStackID::Value> {
378378
IO.enumCase(ID, "default", TargetStackID::Default);
379379
IO.enumCase(ID, "sgpr-spill", TargetStackID::SGPRSpill);
380380
IO.enumCase(ID, "scalable-vector", TargetStackID::ScalableVector);
381+
IO.enumCase(ID, "scalable-pred-vector", TargetStackID::ScalablePredVector);
381382
IO.enumCase(ID, "wasm-local", TargetStackID::WasmLocal);
382383
IO.enumCase(ID, "noalloc", TargetStackID::NoAlloc);
383384
}

‎llvm/include/llvm/CodeGen/MachineFrameInfo.h

Lines changed: 8 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -494,7 +494,14 @@ class MachineFrameInfo {
494494
/// Should this stack ID be considered in MaxAlignment.
495495
bool contributesToMaxAlignment(uint8_t StackID) {
496496
return StackID == TargetStackID::Default ||
497-
StackID == TargetStackID::ScalableVector;
497+
StackID == TargetStackID::ScalableVector ||
498+
StackID == TargetStackID::ScalablePredVector;
499+
}
500+
501+
bool isScalableStackID(int ObjectIdx) const {
502+
uint8_t StackID = getStackID(ObjectIdx);
503+
return StackID == TargetStackID::ScalableVector ||
504+
StackID == TargetStackID::ScalablePredVector;
498505
}
499506

500507
/// setObjectAlignment - Change the alignment of the specified stack object.

‎llvm/include/llvm/CodeGen/TargetFrameLowering.h

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -32,6 +32,7 @@ enum Value {
3232
SGPRSpill = 1,
3333
ScalableVector = 2,
3434
WasmLocal = 3,
35+
ScalablePredVector = 4,
3536
NoAlloc = 255
3637
};
3738
}

‎llvm/lib/CodeGen/StackFrameLayoutAnalysisPass.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -72,7 +72,7 @@ struct StackFrameLayoutAnalysis {
7272
: Slot(Idx), Size(MFI.getObjectSize(Idx)),
7373
Align(MFI.getObjectAlign(Idx).value()), Offset(Offset),
7474
SlotTy(Invalid), Scalable(false) {
75-
Scalable = MFI.getStackID(Idx) == TargetStackID::ScalableVector;
75+
Scalable = MFI.isScalableStackID(Idx);
7676
if (MFI.isSpillSlotObjectIndex(Idx))
7777
SlotTy = SlotType::Spill;
7878
else if (MFI.isFixedObjectIndex(Idx))

‎llvm/lib/Target/AArch64/AArch64FrameLowering.cpp

Lines changed: 16 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -610,7 +610,7 @@ void AArch64FrameLowering::emitCalleeSavedGPRLocations(
610610
CFIInstBuilder CFIBuilder(MBB, MBBI, MachineInstr::FrameSetup);
611611
for (const auto &Info : CSI) {
612612
unsigned FrameIdx = Info.getFrameIdx();
613-
if (MFI.getStackID(FrameIdx) == TargetStackID::ScalableVector)
613+
if (MFI.isScalableStackID(FrameIdx))
614614
continue;
615615

616616
assert(!Info.isSpilledToReg() && "Spilling to registers not implemented");
@@ -643,7 +643,7 @@ void AArch64FrameLowering::emitCalleeSavedSVELocations(
643643
CFIInstBuilder CFIBuilder(MBB, MBBI, MachineInstr::FrameSetup);
644644

645645
for (const auto &Info : CSI) {
646-
if (!(MFI.getStackID(Info.getFrameIdx()) == TargetStackID::ScalableVector))
646+
if (!MFI.isScalableStackID(Info.getFrameIdx()))
647647
continue;
648648

649649
// Not all unwinders may know about SVE registers, so assume the lowest
@@ -710,8 +710,7 @@ static void emitCalleeSavedRestores(MachineBasicBlock &MBB,
710710
CFIInstBuilder CFIBuilder(MBB, MBBI, MachineInstr::FrameDestroy);
711711

712712
for (const auto &Info : CSI) {
713-
if (SVE !=
714-
(MFI.getStackID(Info.getFrameIdx()) == TargetStackID::ScalableVector))
713+
if (SVE != MFI.isScalableStackID(Info.getFrameIdx()))
715714
continue;
716715

717716
MCRegister Reg = Info.getReg();
@@ -2693,7 +2692,7 @@ AArch64FrameLowering::getFrameIndexReferenceFromSP(const MachineFunction &MF,
26932692
const auto *AFI = MF.getInfo<AArch64FunctionInfo>();
26942693
bool FPAfterSVECalleeSaves =
26952694
isTargetWindows(MF) && AFI->getSVECalleeSavedStackSize();
2696-
if (MFI.getStackID(FI) == TargetStackID::ScalableVector) {
2695+
if (MFI.isScalableStackID(FI)) {
26972696
if (FPAfterSVECalleeSaves &&
26982697
-ObjectOffset <= (int64_t)AFI->getSVECalleeSavedStackSize())
26992698
return StackOffset::getScalable(ObjectOffset);
@@ -2759,7 +2758,7 @@ StackOffset AArch64FrameLowering::resolveFrameIndexReference(
27592758
const auto &MFI = MF.getFrameInfo();
27602759
int64_t ObjectOffset = MFI.getObjectOffset(FI);
27612760
bool isFixed = MFI.isFixedObjectIndex(FI);
2762-
bool isSVE = MFI.getStackID(FI) == TargetStackID::ScalableVector;
2761+
bool isSVE = MFI.isScalableStackID(FI);
27632762
return resolveFrameOffsetReference(MF, ObjectOffset, isFixed, isSVE, FrameReg,
27642763
PreferFP, ForSimm);
27652764
}
@@ -3495,10 +3494,14 @@ bool AArch64FrameLowering::spillCalleeSavedRegisters(
34953494
}
34963495
// Update the StackIDs of the SVE stack slots.
34973496
MachineFrameInfo &MFI = MF.getFrameInfo();
3498-
if (RPI.Type == RegPairInfo::ZPR || RPI.Type == RegPairInfo::PPR) {
3497+
if (RPI.Type == RegPairInfo::ZPR) {
34993498
MFI.setStackID(FrameIdxReg1, TargetStackID::ScalableVector);
35003499
if (RPI.isPaired())
35013500
MFI.setStackID(FrameIdxReg2, TargetStackID::ScalableVector);
3501+
} else if (RPI.Type == RegPairInfo::PPR) {
3502+
MFI.setStackID(FrameIdxReg1, TargetStackID::ScalablePredVector);
3503+
if (RPI.isPaired())
3504+
MFI.setStackID(FrameIdxReg2, TargetStackID::ScalablePredVector);
35023505
}
35033506

35043507
if (X0Scratch != AArch64::NoRegister)
@@ -3713,8 +3716,7 @@ void AArch64FrameLowering::determineStackHazardSlot(
37133716
for (auto &MI : MBB) {
37143717
std::optional<int> FI = getLdStFrameID(MI, MFI);
37153718
if (FI && *FI >= 0 && *FI < (int)FrameObjects.size()) {
3716-
if (MFI.getStackID(*FI) == TargetStackID::ScalableVector ||
3717-
AArch64InstrInfo::isFpOrNEON(MI))
3719+
if (MFI.isScalableStackID(*FI) || AArch64InstrInfo::isFpOrNEON(MI))
37183720
FrameObjects[*FI] |= 2;
37193721
else
37203722
FrameObjects[*FI] |= 1;
@@ -4176,7 +4178,7 @@ static int64_t determineSVEStackObjectOffsets(MachineFrameInfo &MFI,
41764178
#ifndef NDEBUG
41774179
// First process all fixed stack objects.
41784180
for (int I = MFI.getObjectIndexBegin(); I != 0; ++I)
4179-
assert(MFI.getStackID(I) != TargetStackID::ScalableVector &&
4181+
assert(!MFI.isScalableStackID(I) &&
41804182
"SVE vectors should never be passed on the stack by value, only by "
41814183
"reference.");
41824184
#endif
@@ -4210,12 +4212,11 @@ static int64_t determineSVEStackObjectOffsets(MachineFrameInfo &MFI,
42104212
int StackProtectorFI = -1;
42114213
if (MFI.hasStackProtectorIndex()) {
42124214
StackProtectorFI = MFI.getStackProtectorIndex();
4213-
if (MFI.getStackID(StackProtectorFI) == TargetStackID::ScalableVector)
4215+
if (MFI.isScalableStackID(StackProtectorFI))
42144216
ObjectsToAllocate.push_back(StackProtectorFI);
42154217
}
42164218
for (int I = 0, E = MFI.getObjectIndexEnd(); I != E; ++I) {
4217-
unsigned StackID = MFI.getStackID(I);
4218-
if (StackID != TargetStackID::ScalableVector)
4219+
if (!MFI.isScalableStackID(I))
42194220
continue;
42204221
if (I == StackProtectorFI)
42214222
continue;
@@ -5230,8 +5231,7 @@ void AArch64FrameLowering::orderFrameObjects(
52305231
if (AFI.hasStackHazardSlotIndex()) {
52315232
std::optional<int> FI = getLdStFrameID(MI, MFI);
52325233
if (FI && *FI >= 0 && *FI < (int)FrameObjects.size()) {
5233-
if (MFI.getStackID(*FI) == TargetStackID::ScalableVector ||
5234-
AArch64InstrInfo::isFpOrNEON(MI))
5234+
if (MFI.isScalableStackID(*FI) || AArch64InstrInfo::isFpOrNEON(MI))
52355235
FrameObjects[*FI].Accesses |= FrameObject::AccessFPR;
52365236
else
52375237
FrameObjects[*FI].Accesses |= FrameObject::AccessGPR;
@@ -5589,7 +5589,7 @@ void AArch64FrameLowering::emitRemarks(
55895589
}
55905590

55915591
unsigned RegTy = StackAccess::AccessType::GPR;
5592-
if (MFI.getStackID(FrameIdx) == TargetStackID::ScalableVector) {
5592+
if (MFI.isScalableStackID(FrameIdx)) {
55935593
// SPILL_PPR_TO_ZPR_SLOT_PSEUDO and FILL_PPR_FROM_ZPR_SLOT_PSEUDO
55945594
// spill/fill the predicate as a data vector (so are an FPR acess).
55955595
if (MI.getOpcode() != AArch64::SPILL_PPR_TO_ZPR_SLOT_PSEUDO &&

‎llvm/lib/Target/AArch64/AArch64FrameLowering.h

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -111,6 +111,7 @@ class AArch64FrameLowering : public TargetFrameLowering {
111111
return false;
112112
case TargetStackID::Default:
113113
case TargetStackID::ScalableVector:
114+
case TargetStackID::ScalablePredVector:
114115
case TargetStackID::NoAlloc:
115116
return true;
116117
}
@@ -119,7 +120,8 @@ class AArch64FrameLowering : public TargetFrameLowering {
119120
bool isStackIdSafeForLocalArea(unsigned StackId) const override {
120121
// We don't support putting SVE objects into the pre-allocated local
121122
// frame block at the moment.
122-
return StackId != TargetStackID::ScalableVector;
123+
return (StackId != TargetStackID::ScalableVector &&
124+
StackId != TargetStackID::ScalablePredVector);
123125
}
124126

125127
void

‎llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -7375,7 +7375,7 @@ bool AArch64DAGToDAGISel::SelectAddrModeIndexedSVE(SDNode *Root, SDValue N,
73757375
int FI = cast<FrameIndexSDNode>(N)->getIndex();
73767376
// We can only encode VL scaled offsets, so only fold in frame indexes
73777377
// referencing SVE objects.
7378-
if (MFI.getStackID(FI) == TargetStackID::ScalableVector) {
7378+
if (MFI.isScalableStackID(FI)) {
73797379
Base = CurDAG->getTargetFrameIndex(FI, TLI->getPointerTy(DL));
73807380
OffImm = CurDAG->getTargetConstant(0, SDLoc(N), MVT::i64);
73817381
return true;
@@ -7421,7 +7421,7 @@ bool AArch64DAGToDAGISel::SelectAddrModeIndexedSVE(SDNode *Root, SDValue N,
74217421
int FI = cast<FrameIndexSDNode>(Base)->getIndex();
74227422
// We can only encode VL scaled offsets, so only fold in frame indexes
74237423
// referencing SVE objects.
7424-
if (MFI.getStackID(FI) == TargetStackID::ScalableVector)
7424+
if (MFI.isScalableStackID(FI))
74257425
Base = CurDAG->getTargetFrameIndex(FI, TLI->getPointerTy(DL));
74267426
}
74277427

‎llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

Lines changed: 8 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -8681,8 +8681,7 @@ void AArch64TargetLowering::AdjustInstrPostInstrSelection(MachineInstr &MI,
86818681
(MI.getOpcode() == AArch64::ADDXri ||
86828682
MI.getOpcode() == AArch64::SUBXri)) {
86838683
const MachineOperand &MO = MI.getOperand(1);
8684-
if (MO.isFI() && MF.getFrameInfo().getStackID(MO.getIndex()) ==
8685-
TargetStackID::ScalableVector)
8684+
if (MO.isFI() && MF.getFrameInfo().isScalableStackID(MO.getIndex()))
86868685
MI.addOperand(MachineOperand::CreateReg(AArch64::VG, /*IsDef=*/false,
86878686
/*IsImplicit=*/true));
86888687
}
@@ -9079,8 +9078,12 @@ AArch64TargetLowering::LowerCall(CallLoweringInfo &CLI,
90799078
Align Alignment = DAG.getDataLayout().getPrefTypeAlign(Ty);
90809079
MachineFrameInfo &MFI = MF.getFrameInfo();
90819080
int FI = MFI.CreateStackObject(StoreSize, Alignment, false);
9082-
if (isScalable)
9083-
MFI.setStackID(FI, TargetStackID::ScalableVector);
9081+
if (isScalable) {
9082+
bool IsPred = VA.getValVT() == MVT::aarch64svcount ||
9083+
VA.getValVT().getVectorElementType() == MVT::i1;
9084+
MFI.setStackID(FI, IsPred ? TargetStackID::ScalablePredVector
9085+
: TargetStackID::ScalableVector);
9086+
}
90849087

90859088
MachinePointerInfo MPI = MachinePointerInfo::getFixedStack(MF, FI);
90869089
SDValue Ptr = DAG.getFrameIndex(
@@ -28221,7 +28224,7 @@ void AArch64TargetLowering::finalizeLowering(MachineFunction &MF) const {
2822128224
// than doing it here in finalizeLowering.
2822228225
if (MFI.hasStackProtectorIndex()) {
2822328226
for (unsigned int i = 0, e = MFI.getObjectIndexEnd(); i != e; ++i) {
28224-
if (MFI.getStackID(i) == TargetStackID::ScalableVector &&
28227+
if (MFI.isScalableStackID(i) &&
2822528228
MFI.getObjectSSPLayout(i) != MachineFrameInfo::SSPLK_None) {
2822628229
MFI.setStackID(MFI.getStackProtectorIndex(),
2822728230
TargetStackID::ScalableVector);

‎llvm/lib/Target/AArch64/AArch64InstrInfo.cpp

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -5426,7 +5426,7 @@ void AArch64InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
54265426
assert(Subtarget.isSVEorStreamingSVEAvailable() &&
54275427
"Unexpected register store without SVE store instructions");
54285428
Opc = AArch64::STR_PXI;
5429-
StackID = TargetStackID::ScalableVector;
5429+
StackID = TargetStackID::ScalablePredVector;
54305430
}
54315431
break;
54325432
}
@@ -5441,7 +5441,7 @@ void AArch64InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
54415441
Opc = AArch64::STRSui;
54425442
else if (AArch64::PPR2RegClass.hasSubClassEq(RC)) {
54435443
Opc = AArch64::STR_PPXI;
5444-
StackID = TargetStackID::ScalableVector;
5444+
StackID = TargetStackID::ScalablePredVector;
54455445
}
54465446
break;
54475447
case 8:
@@ -5603,7 +5603,7 @@ void AArch64InstrInfo::loadRegFromStackSlot(
56035603
if (IsPNR)
56045604
PNRReg = DestReg;
56055605
Opc = AArch64::LDR_PXI;
5606-
StackID = TargetStackID::ScalableVector;
5606+
StackID = TargetStackID::ScalablePredVector;
56075607
}
56085608
break;
56095609
}
@@ -5618,7 +5618,7 @@ void AArch64InstrInfo::loadRegFromStackSlot(
56185618
Opc = AArch64::LDRSui;
56195619
else if (AArch64::PPR2RegClass.hasSubClassEq(RC)) {
56205620
Opc = AArch64::LDR_PPXI;
5621-
StackID = TargetStackID::ScalableVector;
5621+
StackID = TargetStackID::ScalablePredVector;
56225622
}
56235623
break;
56245624
case 8:

‎llvm/test/CodeGen/AArch64/debug-info-sve-dbg-declare.mir

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -164,10 +164,10 @@ stack:
164164
- { id: 1, name: z1.addr, size: 16, alignment: 16, stack-id: scalable-vector,
165165
debug-info-variable: '!31', debug-info-expression: '!DIExpression()',
166166
debug-info-location: '!32' }
167-
- { id: 2, name: p0.addr, size: 2, alignment: 2, stack-id: scalable-vector,
167+
- { id: 2, name: p0.addr, size: 2, alignment: 2, stack-id: scalable-pred-vector,
168168
debug-info-variable: '!33', debug-info-expression: '!DIExpression()',
169169
debug-info-location: '!34' }
170-
- { id: 3, name: p1.addr, size: 2, alignment: 2, stack-id: scalable-vector,
170+
- { id: 3, name: p1.addr, size: 2, alignment: 2, stack-id: scalable-pred-vector,
171171
debug-info-variable: '!35', debug-info-expression: '!DIExpression()',
172172
debug-info-location: '!36' }
173173
- { id: 4, name: w0.addr, size: 4, alignment: 4, local-offset: -4, debug-info-variable: '!37',
@@ -181,10 +181,10 @@ stack:
181181
- { id: 7, name: localv1, size: 16, alignment: 16, stack-id: scalable-vector,
182182
debug-info-variable: '!45', debug-info-expression: '!DIExpression()',
183183
debug-info-location: '!46' }
184-
- { id: 8, name: localp0, size: 2, alignment: 2, stack-id: scalable-vector,
184+
- { id: 8, name: localp0, size: 2, alignment: 2, stack-id: scalable-pred-vector,
185185
debug-info-variable: '!48', debug-info-expression: '!DIExpression()',
186186
debug-info-location: '!49' }
187-
- { id: 9, name: localp1, size: 2, alignment: 2, stack-id: scalable-vector,
187+
- { id: 9, name: localp1, size: 2, alignment: 2, stack-id: scalable-pred-vector,
188188
debug-info-variable: '!51', debug-info-expression: '!DIExpression()',
189189
debug-info-location: '!52' }
190190
machineFunctionInfo: {}

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