Skip to content

Commit 7e41c7c

Browse files
MacDueMacDue
committed
[Codegen] Add a separate stack ID for scalable predicates
This splits out "ScalablePredVector" from the "ScalableVector" StackID this is primarily to allow easy differentiation between vectors and predicates (without inspecting instructions). This new stack ID is not used in many places yet, but will be used in a later patch to mark stack slots that are known to contain predicates.
1 parent 9fde72e commit 7e41c7c

14 files changed

+66
-52
lines changed

‎llvm/include/llvm/CodeGen/MIRYamlMapping.h

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -378,6 +378,7 @@ struct ScalarEnumerationTraits<TargetStackID::Value> {
378378
IO.enumCase(ID, "default", TargetStackID::Default);
379379
IO.enumCase(ID, "sgpr-spill", TargetStackID::SGPRSpill);
380380
IO.enumCase(ID, "scalable-vector", TargetStackID::ScalableVector);
381+
IO.enumCase(ID, "scalable-pred-vector", TargetStackID::ScalablePredVector);
381382
IO.enumCase(ID, "wasm-local", TargetStackID::WasmLocal);
382383
IO.enumCase(ID, "noalloc", TargetStackID::NoAlloc);
383384
}

‎llvm/include/llvm/CodeGen/MachineFrameInfo.h

Lines changed: 8 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -494,7 +494,14 @@ class MachineFrameInfo {
494494
/// Should this stack ID be considered in MaxAlignment.
495495
bool contributesToMaxAlignment(uint8_t StackID) {
496496
return StackID == TargetStackID::Default ||
497-
StackID == TargetStackID::ScalableVector;
497+
StackID == TargetStackID::ScalableVector ||
498+
StackID == TargetStackID::ScalablePredVector;
499+
}
500+
501+
bool isScalableStackID(int ObjectIdx) const {
502+
uint8_t StackID = getStackID(ObjectIdx);
503+
return StackID == TargetStackID::ScalableVector ||
504+
StackID == TargetStackID::ScalablePredVector;
498505
}
499506

500507
/// setObjectAlignment - Change the alignment of the specified stack object.

‎llvm/include/llvm/CodeGen/TargetFrameLowering.h

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -32,6 +32,7 @@ enum Value {
3232
SGPRSpill = 1,
3333
ScalableVector = 2,
3434
WasmLocal = 3,
35+
ScalablePredVector = 4,
3536
NoAlloc = 255
3637
};
3738
}

‎llvm/lib/CodeGen/StackFrameLayoutAnalysisPass.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -72,7 +72,7 @@ struct StackFrameLayoutAnalysis {
7272
: Slot(Idx), Size(MFI.getObjectSize(Idx)),
7373
Align(MFI.getObjectAlign(Idx).value()), Offset(Offset),
7474
SlotTy(Invalid), Scalable(false) {
75-
Scalable = MFI.getStackID(Idx) == TargetStackID::ScalableVector;
75+
Scalable = MFI.isScalableStackID(Idx);
7676
if (MFI.isSpillSlotObjectIndex(Idx))
7777
SlotTy = SlotType::Spill;
7878
else if (MFI.isFixedObjectIndex(Idx))

‎llvm/lib/Target/AArch64/AArch64FrameLowering.cpp

Lines changed: 16 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -612,7 +612,7 @@ void AArch64FrameLowering::emitCalleeSavedGPRLocations(
612612
CFIInstBuilder CFIBuilder(MBB, MBBI, MachineInstr::FrameSetup);
613613
for (const auto &Info : CSI) {
614614
unsigned FrameIdx = Info.getFrameIdx();
615-
if (MFI.getStackID(FrameIdx) == TargetStackID::ScalableVector)
615+
if (MFI.isScalableStackID(FrameIdx))
616616
continue;
617617

618618
assert(!Info.isSpilledToReg() && "Spilling to registers not implemented");
@@ -645,7 +645,7 @@ void AArch64FrameLowering::emitCalleeSavedSVELocations(
645645
CFIInstBuilder CFIBuilder(MBB, MBBI, MachineInstr::FrameSetup);
646646

647647
for (const auto &Info : CSI) {
648-
if (!(MFI.getStackID(Info.getFrameIdx()) == TargetStackID::ScalableVector))
648+
if (!MFI.isScalableStackID(Info.getFrameIdx()))
649649
continue;
650650

651651
// Not all unwinders may know about SVE registers, so assume the lowest
@@ -712,8 +712,7 @@ static void emitCalleeSavedRestores(MachineBasicBlock &MBB,
712712
CFIInstBuilder CFIBuilder(MBB, MBBI, MachineInstr::FrameDestroy);
713713

714714
for (const auto &Info : CSI) {
715-
if (SVE !=
716-
(MFI.getStackID(Info.getFrameIdx()) == TargetStackID::ScalableVector))
715+
if (SVE != MFI.isScalableStackID(Info.getFrameIdx()))
717716
continue;
718717

719718
MCRegister Reg = Info.getReg();
@@ -2749,7 +2748,7 @@ AArch64FrameLowering::getFrameIndexReferenceFromSP(const MachineFunction &MF,
27492748
const auto *AFI = MF.getInfo<AArch64FunctionInfo>();
27502749
bool FPAfterSVECalleeSaves =
27512750
isTargetWindows(MF) && AFI->getSVECalleeSavedStackSize();
2752-
if (MFI.getStackID(FI) == TargetStackID::ScalableVector) {
2751+
if (MFI.isScalableStackID(FI)) {
27532752
if (FPAfterSVECalleeSaves &&
27542753
-ObjectOffset <= (int64_t)AFI->getSVECalleeSavedStackSize())
27552754
return StackOffset::getScalable(ObjectOffset);
@@ -2815,7 +2814,7 @@ StackOffset AArch64FrameLowering::resolveFrameIndexReference(
28152814
const auto &MFI = MF.getFrameInfo();
28162815
int64_t ObjectOffset = MFI.getObjectOffset(FI);
28172816
bool isFixed = MFI.isFixedObjectIndex(FI);
2818-
bool isSVE = MFI.getStackID(FI) == TargetStackID::ScalableVector;
2817+
bool isSVE = MFI.isScalableStackID(FI);
28192818
return resolveFrameOffsetReference(MF, ObjectOffset, isFixed, isSVE, FrameReg,
28202819
PreferFP, ForSimm);
28212820
}
@@ -3551,10 +3550,14 @@ bool AArch64FrameLowering::spillCalleeSavedRegisters(
35513550
}
35523551
// Update the StackIDs of the SVE stack slots.
35533552
MachineFrameInfo &MFI = MF.getFrameInfo();
3554-
if (RPI.Type == RegPairInfo::ZPR || RPI.Type == RegPairInfo::PPR) {
3553+
if (RPI.Type == RegPairInfo::ZPR) {
35553554
MFI.setStackID(FrameIdxReg1, TargetStackID::ScalableVector);
35563555
if (RPI.isPaired())
35573556
MFI.setStackID(FrameIdxReg2, TargetStackID::ScalableVector);
3557+
} else if (RPI.Type == RegPairInfo::PPR) {
3558+
MFI.setStackID(FrameIdxReg1, TargetStackID::ScalablePredVector);
3559+
if (RPI.isPaired())
3560+
MFI.setStackID(FrameIdxReg2, TargetStackID::ScalablePredVector);
35583561
}
35593562

35603563
if (X0Scratch != AArch64::NoRegister)
@@ -3769,8 +3772,7 @@ void AArch64FrameLowering::determineStackHazardSlot(
37693772
for (auto &MI : MBB) {
37703773
std::optional<int> FI = getLdStFrameID(MI, MFI);
37713774
if (FI && *FI >= 0 && *FI < (int)FrameObjects.size()) {
3772-
if (MFI.getStackID(*FI) == TargetStackID::ScalableVector ||
3773-
AArch64InstrInfo::isFpOrNEON(MI))
3775+
if (MFI.isScalableStackID(*FI) || AArch64InstrInfo::isFpOrNEON(MI))
37743776
FrameObjects[*FI] |= 2;
37753777
else
37763778
FrameObjects[*FI] |= 1;
@@ -4232,7 +4234,7 @@ static int64_t determineSVEStackObjectOffsets(MachineFrameInfo &MFI,
42324234
#ifndef NDEBUG
42334235
// First process all fixed stack objects.
42344236
for (int I = MFI.getObjectIndexBegin(); I != 0; ++I)
4235-
assert(MFI.getStackID(I) != TargetStackID::ScalableVector &&
4237+
assert(!MFI.isScalableStackID(I) &&
42364238
"SVE vectors should never be passed on the stack by value, only by "
42374239
"reference.");
42384240
#endif
@@ -4266,12 +4268,11 @@ static int64_t determineSVEStackObjectOffsets(MachineFrameInfo &MFI,
42664268
int StackProtectorFI = -1;
42674269
if (MFI.hasStackProtectorIndex()) {
42684270
StackProtectorFI = MFI.getStackProtectorIndex();
4269-
if (MFI.getStackID(StackProtectorFI) == TargetStackID::ScalableVector)
4271+
if (MFI.isScalableStackID(StackProtectorFI))
42704272
ObjectsToAllocate.push_back(StackProtectorFI);
42714273
}
42724274
for (int I = 0, E = MFI.getObjectIndexEnd(); I != E; ++I) {
4273-
unsigned StackID = MFI.getStackID(I);
4274-
if (StackID != TargetStackID::ScalableVector)
4275+
if (!MFI.isScalableStackID(I))
42754276
continue;
42764277
if (I == StackProtectorFI)
42774278
continue;
@@ -5286,8 +5287,7 @@ void AArch64FrameLowering::orderFrameObjects(
52865287
if (AFI.hasStackHazardSlotIndex()) {
52875288
std::optional<int> FI = getLdStFrameID(MI, MFI);
52885289
if (FI && *FI >= 0 && *FI < (int)FrameObjects.size()) {
5289-
if (MFI.getStackID(*FI) == TargetStackID::ScalableVector ||
5290-
AArch64InstrInfo::isFpOrNEON(MI))
5290+
if (MFI.isScalableStackID(*FI) || AArch64InstrInfo::isFpOrNEON(MI))
52915291
FrameObjects[*FI].Accesses |= FrameObject::AccessFPR;
52925292
else
52935293
FrameObjects[*FI].Accesses |= FrameObject::AccessGPR;
@@ -5645,7 +5645,7 @@ void AArch64FrameLowering::emitRemarks(
56455645
}
56465646

56475647
unsigned RegTy = StackAccess::AccessType::GPR;
5648-
if (MFI.getStackID(FrameIdx) == TargetStackID::ScalableVector) {
5648+
if (MFI.isScalableStackID(FrameIdx)) {
56495649
// SPILL_PPR_TO_ZPR_SLOT_PSEUDO and FILL_PPR_FROM_ZPR_SLOT_PSEUDO
56505650
// spill/fill the predicate as a data vector (so are an FPR access).
56515651
if (MI.getOpcode() != AArch64::SPILL_PPR_TO_ZPR_SLOT_PSEUDO &&

‎llvm/lib/Target/AArch64/AArch64FrameLowering.h

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -111,6 +111,7 @@ class AArch64FrameLowering : public TargetFrameLowering {
111111
return false;
112112
case TargetStackID::Default:
113113
case TargetStackID::ScalableVector:
114+
case TargetStackID::ScalablePredVector:
114115
case TargetStackID::NoAlloc:
115116
return true;
116117
}
@@ -119,7 +120,8 @@ class AArch64FrameLowering : public TargetFrameLowering {
119120
bool isStackIdSafeForLocalArea(unsigned StackId) const override {
120121
// We don't support putting SVE objects into the pre-allocated local
121122
// frame block at the moment.
122-
return StackId != TargetStackID::ScalableVector;
123+
return (StackId != TargetStackID::ScalableVector &&
124+
StackId != TargetStackID::ScalablePredVector);
123125
}
124126

125127
void

‎llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -7487,7 +7487,7 @@ bool AArch64DAGToDAGISel::SelectAddrModeIndexedSVE(SDNode *Root, SDValue N,
74877487
int FI = cast<FrameIndexSDNode>(N)->getIndex();
74887488
// We can only encode VL scaled offsets, so only fold in frame indexes
74897489
// referencing SVE objects.
7490-
if (MFI.getStackID(FI) == TargetStackID::ScalableVector) {
7490+
if (MFI.isScalableStackID(FI)) {
74917491
Base = CurDAG->getTargetFrameIndex(FI, TLI->getPointerTy(DL));
74927492
OffImm = CurDAG->getTargetConstant(0, SDLoc(N), MVT::i64);
74937493
return true;
@@ -7533,7 +7533,7 @@ bool AArch64DAGToDAGISel::SelectAddrModeIndexedSVE(SDNode *Root, SDValue N,
75337533
int FI = cast<FrameIndexSDNode>(Base)->getIndex();
75347534
// We can only encode VL scaled offsets, so only fold in frame indexes
75357535
// referencing SVE objects.
7536-
if (MFI.getStackID(FI) == TargetStackID::ScalableVector)
7536+
if (MFI.isScalableStackID(FI))
75377537
Base = CurDAG->getTargetFrameIndex(FI, TLI->getPointerTy(DL));
75387538
}
75397539

‎llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

Lines changed: 8 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -8713,8 +8713,7 @@ void AArch64TargetLowering::AdjustInstrPostInstrSelection(MachineInstr &MI,
87138713
(MI.getOpcode() == AArch64::ADDXri ||
87148714
MI.getOpcode() == AArch64::SUBXri)) {
87158715
const MachineOperand &MO = MI.getOperand(1);
8716-
if (MO.isFI() && MF.getFrameInfo().getStackID(MO.getIndex()) ==
8717-
TargetStackID::ScalableVector)
8716+
if (MO.isFI() && MF.getFrameInfo().isScalableStackID(MO.getIndex()))
87188717
MI.addOperand(MachineOperand::CreateReg(AArch64::VG, /*IsDef=*/false,
87198718
/*IsImplicit=*/true));
87208719
}
@@ -9150,8 +9149,12 @@ AArch64TargetLowering::LowerCall(CallLoweringInfo &CLI,
91509149
Align Alignment = DAG.getDataLayout().getPrefTypeAlign(Ty);
91519150
MachineFrameInfo &MFI = MF.getFrameInfo();
91529151
int FI = MFI.CreateStackObject(StoreSize, Alignment, false);
9153-
if (isScalable)
9154-
MFI.setStackID(FI, TargetStackID::ScalableVector);
9152+
if (isScalable) {
9153+
bool IsPred = VA.getValVT() == MVT::aarch64svcount ||
9154+
VA.getValVT().getVectorElementType() == MVT::i1;
9155+
MFI.setStackID(FI, IsPred ? TargetStackID::ScalablePredVector
9156+
: TargetStackID::ScalableVector);
9157+
}
91559158

91569159
MachinePointerInfo MPI = MachinePointerInfo::getFixedStack(MF, FI);
91579160
SDValue Ptr = DAG.getFrameIndex(
@@ -28500,7 +28503,7 @@ void AArch64TargetLowering::finalizeLowering(MachineFunction &MF) const {
2850028503
// than doing it here in finalizeLowering.
2850128504
if (MFI.hasStackProtectorIndex()) {
2850228505
for (unsigned int i = 0, e = MFI.getObjectIndexEnd(); i != e; ++i) {
28503-
if (MFI.getStackID(i) == TargetStackID::ScalableVector &&
28506+
if (MFI.isScalableStackID(i) &&
2850428507
MFI.getObjectSSPLayout(i) != MachineFrameInfo::SSPLK_None) {
2850528508
MFI.setStackID(MFI.getStackProtectorIndex(),
2850628509
TargetStackID::ScalableVector);

‎llvm/lib/Target/AArch64/AArch64InstrInfo.cpp

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -5435,7 +5435,7 @@ void AArch64InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
54355435
assert(Subtarget.isSVEorStreamingSVEAvailable() &&
54365436
"Unexpected register store without SVE store instructions");
54375437
Opc = AArch64::STR_PXI;
5438-
StackID = TargetStackID::ScalableVector;
5438+
StackID = TargetStackID::ScalablePredVector;
54395439
}
54405440
break;
54415441
}
@@ -5450,7 +5450,7 @@ void AArch64InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
54505450
Opc = AArch64::STRSui;
54515451
else if (AArch64::PPR2RegClass.hasSubClassEq(RC)) {
54525452
Opc = AArch64::STR_PPXI;
5453-
StackID = TargetStackID::ScalableVector;
5453+
StackID = TargetStackID::ScalablePredVector;
54545454
}
54555455
break;
54565456
case 8:
@@ -5612,7 +5612,7 @@ void AArch64InstrInfo::loadRegFromStackSlot(
56125612
if (IsPNR)
56135613
PNRReg = DestReg;
56145614
Opc = AArch64::LDR_PXI;
5615-
StackID = TargetStackID::ScalableVector;
5615+
StackID = TargetStackID::ScalablePredVector;
56165616
}
56175617
break;
56185618
}
@@ -5627,7 +5627,7 @@ void AArch64InstrInfo::loadRegFromStackSlot(
56275627
Opc = AArch64::LDRSui;
56285628
else if (AArch64::PPR2RegClass.hasSubClassEq(RC)) {
56295629
Opc = AArch64::LDR_PPXI;
5630-
StackID = TargetStackID::ScalableVector;
5630+
StackID = TargetStackID::ScalablePredVector;
56315631
}
56325632
break;
56335633
case 8:

‎llvm/test/CodeGen/AArch64/debug-info-sve-dbg-declare.mir

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -164,10 +164,10 @@ stack:
164164
- { id: 1, name: z1.addr, size: 16, alignment: 16, stack-id: scalable-vector,
165165
debug-info-variable: '!31', debug-info-expression: '!DIExpression()',
166166
debug-info-location: '!32' }
167-
- { id: 2, name: p0.addr, size: 2, alignment: 2, stack-id: scalable-vector,
167+
- { id: 2, name: p0.addr, size: 2, alignment: 2, stack-id: scalable-pred-vector,
168168
debug-info-variable: '!33', debug-info-expression: '!DIExpression()',
169169
debug-info-location: '!34' }
170-
- { id: 3, name: p1.addr, size: 2, alignment: 2, stack-id: scalable-vector,
170+
- { id: 3, name: p1.addr, size: 2, alignment: 2, stack-id: scalable-pred-vector,
171171
debug-info-variable: '!35', debug-info-expression: '!DIExpression()',
172172
debug-info-location: '!36' }
173173
- { id: 4, name: w0.addr, size: 4, alignment: 4, local-offset: -4, debug-info-variable: '!37',
@@ -181,10 +181,10 @@ stack:
181181
- { id: 7, name: localv1, size: 16, alignment: 16, stack-id: scalable-vector,
182182
debug-info-variable: '!45', debug-info-expression: '!DIExpression()',
183183
debug-info-location: '!46' }
184-
- { id: 8, name: localp0, size: 2, alignment: 2, stack-id: scalable-vector,
184+
- { id: 8, name: localp0, size: 2, alignment: 2, stack-id: scalable-pred-vector,
185185
debug-info-variable: '!48', debug-info-expression: '!DIExpression()',
186186
debug-info-location: '!49' }
187-
- { id: 9, name: localp1, size: 2, alignment: 2, stack-id: scalable-vector,
187+
- { id: 9, name: localp1, size: 2, alignment: 2, stack-id: scalable-pred-vector,
188188
debug-info-variable: '!51', debug-info-expression: '!DIExpression()',
189189
debug-info-location: '!52' }
190190
machineFunctionInfo: {}

0 commit comments

Comments
 (0)