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[msan] Simplify 'maskedCheckAVXIndexShadow' (#147839)
The current instrumentation has more or and element extraction than a coal mine: ``` [[TMP10:%.*]] = extractelement <16 x i32> [[TMP9]], i64 0 [[TMP11:%.*]] = and i32 [[TMP10]], 15 [[TMP43:%.*]] = or i32 [[TMP10]], [[TMP11]] [[TMP12:%.*]] = extractelement <16 x i32> [[TMP9]], i64 1 [[TMP13:%.*]] = and i32 [[TMP12]], 15 [[TMP44:%.*]] = or i32 [[TMP12]], [[TMP13]] ... [[TMP40:%.*]] = extractelement <16 x i32> [[TMP9]], i64 15 [[TMP41:%.*]] = and i32 [[TMP40]], 15 [[TMP57:%.*]] = or i32 [[TMP40]], [[TMP41]] [[_MSCMP:%.*]] = icmp ne i32 [[TMP57]], 0 br i1 [[_MSCMP]], label [[TMP102:%.*]], label [[TMP103:%.*]], !prof [[PROF1]] ``` Simplify it to: ``` [[TMP10:%.*]] = trunc <16 x i32> [[T]] to <16 x i4> [[TMP12:%.*]] = bitcast <16 x i4> [[TMP10]] to i64 [[_MSCMP:%.*]] = icmp ne i64 [[TMP12]], 0 br i1 [[_MSCMP]], label %[[BB13:.*]], label %[[BB14:.*]], !prof [[PROF1]] ```
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9 files changed

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lines changed

‎llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp

Lines changed: 16 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -4307,23 +4307,26 @@ struct MemorySanitizerVisitor : public InstVisitor<MemorySanitizerVisitor> {
43074307
setOrigin(&I, PtrSrcOrigin);
43084308
}
43094309

4310+
// Test whether the mask indices are initialized, only checking the bits that
4311+
// are actually used.
4312+
//
4313+
// e.g., if Idx is <32 x i16>, only (log2(32) == 5) bits of each index are
4314+
// used/checked.
43104315
void maskedCheckAVXIndexShadow(IRBuilder<> &IRB, Value *Idx, Instruction *I) {
4316+
assert(isFixedIntVector(Idx));
43114317
auto IdxVectorSize =
43124318
cast<FixedVectorType>(Idx->getType())->getNumElements();
43134319
assert(isPowerOf2_64(IdxVectorSize));
4314-
auto *IdxVectorElemType =
4315-
cast<FixedVectorType>(Idx->getType())->getElementType();
4316-
Constant *IndexBits =
4317-
ConstantInt::get(IdxVectorElemType, IdxVectorSize - 1);
4318-
auto *IdxShadow = getShadow(Idx);
4319-
// Only the low bits of Idx are used.
4320-
Value *V = nullptr;
4321-
for (size_t i = 0; i < IdxVectorSize; ++i) {
4322-
V = IRB.CreateExtractElement(IdxShadow, i);
4323-
assert(V->getType() == IndexBits->getType());
4324-
V = IRB.CreateOr(V, IRB.CreateAnd(V, IndexBits));
4325-
}
4326-
insertCheckShadow(V, getOrigin(Idx), I);
4320+
4321+
// Compiler isn't smart enough, let's help it
4322+
if (auto *ConstantIdx = dyn_cast<Constant>(Idx))
4323+
return;
4324+
4325+
Value *Truncated = IRB.CreateTrunc(
4326+
Idx,
4327+
FixedVectorType::get(Type::getIntNTy(*MS.C, Log2_64(IdxVectorSize)),
4328+
IdxVectorSize));
4329+
insertCheckShadow(Truncated, getOrigin(Idx), I);
43274330
}
43284331

43294332
// Instrument AVX permutation intrinsic.

‎llvm/test/Instrumentation/MemorySanitizer/X86/avx-intrinsics-x86.ll

Lines changed: 34 additions & 94 deletions
Original file line numberDiff line numberDiff line change
@@ -948,23 +948,18 @@ declare <8 x float> @llvm.x86.avx.rsqrt.ps.256(<8 x float>) nounwind readnone
948948
define <2 x double> @test_x86_avx_vpermilvar_pd(<2 x double> %a0, <2 x i64> %a1) #0 {
949949
; CHECK-LABEL: @test_x86_avx_vpermilvar_pd(
950950
; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 8
951-
; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 16) to ptr), align 8
952951
; CHECK-NEXT: call void @llvm.donothing()
953-
; CHECK-NEXT: [[TMP3:%.*]] = extractelement <2 x i64> [[TMP2]], i64 0
954-
; CHECK-NEXT: [[TMP9:%.*]] = and i64 [[TMP3]], 1
955-
; CHECK-NEXT: [[TMP5:%.*]] = or i64 [[TMP3]], [[TMP9]]
956-
; CHECK-NEXT: [[TMP6:%.*]] = extractelement <2 x i64> [[TMP2]], i64 1
957-
; CHECK-NEXT: [[TMP7:%.*]] = and i64 [[TMP6]], 1
958-
; CHECK-NEXT: [[TMP8:%.*]] = or i64 [[TMP6]], [[TMP7]]
952+
; CHECK-NEXT: [[TMP2:%.*]] = trunc <2 x i64> [[A1:%.*]] to <2 x i1>
959953
; CHECK-NEXT: [[A0:%.*]] = bitcast <2 x i64> [[TMP1]] to <2 x double>
960-
; CHECK-NEXT: [[RES:%.*]] = call <2 x double> @llvm.x86.avx.vpermilvar.pd(<2 x double> [[A0]], <2 x i64> [[A1:%.*]])
954+
; CHECK-NEXT: [[RES:%.*]] = call <2 x double> @llvm.x86.avx.vpermilvar.pd(<2 x double> [[A0]], <2 x i64> [[A1]])
961955
; CHECK-NEXT: [[TMP4:%.*]] = bitcast <2 x double> [[RES]] to <2 x i64>
962-
; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP8]], 0
963-
; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP12:%.*]], label [[TMP13:%.*]], !prof [[PROF1]]
964-
; CHECK: 12:
956+
; CHECK-NEXT: [[TMP6:%.*]] = bitcast <2 x i1> [[TMP2]] to i2
957+
; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i2 [[TMP6]], 0
958+
; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP7:%.*]], label [[TMP8:%.*]], !prof [[PROF1]]
959+
; CHECK: 7:
965960
; CHECK-NEXT: call void @__msan_warning_noreturn()
966961
; CHECK-NEXT: unreachable
967-
; CHECK: 13:
962+
; CHECK: 8:
968963
; CHECK-NEXT: [[RES1:%.*]] = call <2 x double> @llvm.x86.avx.vpermilvar.pd(<2 x double> [[A2:%.*]], <2 x i64> [[A1]])
969964
; CHECK-NEXT: store <2 x i64> [[TMP4]], ptr @__msan_retval_tls, align 8
970965
; CHECK-NEXT: ret <2 x double> [[RES1]]
@@ -978,29 +973,18 @@ declare <2 x double> @llvm.x86.avx.vpermilvar.pd(<2 x double>, <2 x i64>) nounwi
978973
define <4 x double> @test_x86_avx_vpermilvar_pd_256(<4 x double> %a0, <4 x i64> %a1) #0 {
979974
; CHECK-LABEL: @test_x86_avx_vpermilvar_pd_256(
980975
; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i64>, ptr @__msan_param_tls, align 8
981-
; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i64>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 32) to ptr), align 8
982976
; CHECK-NEXT: call void @llvm.donothing()
983-
; CHECK-NEXT: [[TMP3:%.*]] = extractelement <4 x i64> [[TMP2]], i64 0
984-
; CHECK-NEXT: [[TMP15:%.*]] = and i64 [[TMP3]], 3
985-
; CHECK-NEXT: [[TMP5:%.*]] = or i64 [[TMP3]], [[TMP15]]
986-
; CHECK-NEXT: [[TMP6:%.*]] = extractelement <4 x i64> [[TMP2]], i64 1
987-
; CHECK-NEXT: [[TMP7:%.*]] = and i64 [[TMP6]], 3
988-
; CHECK-NEXT: [[TMP8:%.*]] = or i64 [[TMP6]], [[TMP7]]
989-
; CHECK-NEXT: [[TMP9:%.*]] = extractelement <4 x i64> [[TMP2]], i64 2
990-
; CHECK-NEXT: [[TMP10:%.*]] = and i64 [[TMP9]], 3
991-
; CHECK-NEXT: [[TMP11:%.*]] = or i64 [[TMP9]], [[TMP10]]
992-
; CHECK-NEXT: [[TMP12:%.*]] = extractelement <4 x i64> [[TMP2]], i64 3
993-
; CHECK-NEXT: [[TMP13:%.*]] = and i64 [[TMP12]], 3
994-
; CHECK-NEXT: [[TMP14:%.*]] = or i64 [[TMP12]], [[TMP13]]
977+
; CHECK-NEXT: [[TMP2:%.*]] = trunc <4 x i64> [[A1:%.*]] to <4 x i2>
995978
; CHECK-NEXT: [[A0:%.*]] = bitcast <4 x i64> [[TMP1]] to <4 x double>
996-
; CHECK-NEXT: [[RES:%.*]] = call <4 x double> @llvm.x86.avx.vpermilvar.pd.256(<4 x double> [[A0]], <4 x i64> [[A1:%.*]])
979+
; CHECK-NEXT: [[RES:%.*]] = call <4 x double> @llvm.x86.avx.vpermilvar.pd.256(<4 x double> [[A0]], <4 x i64> [[A1]])
997980
; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x double> [[RES]] to <4 x i64>
998-
; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP14]], 0
999-
; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP18:%.*]], label [[TMP19:%.*]], !prof [[PROF1]]
1000-
; CHECK: 18:
981+
; CHECK-NEXT: [[TMP6:%.*]] = bitcast <4 x i2> [[TMP2]] to i8
982+
; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i8 [[TMP6]], 0
983+
; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP7:%.*]], label [[TMP8:%.*]], !prof [[PROF1]]
984+
; CHECK: 7:
1001985
; CHECK-NEXT: call void @__msan_warning_noreturn()
1002986
; CHECK-NEXT: unreachable
1003-
; CHECK: 19:
987+
; CHECK: 8:
1004988
; CHECK-NEXT: [[RES1:%.*]] = call <4 x double> @llvm.x86.avx.vpermilvar.pd.256(<4 x double> [[A2:%.*]], <4 x i64> [[A1]])
1005989
; CHECK-NEXT: store <4 x i64> [[TMP4]], ptr @__msan_retval_tls, align 8
1006990
; CHECK-NEXT: ret <4 x double> [[RES1]]
@@ -1028,29 +1012,18 @@ define <4 x double> @test_x86_avx_vpermilvar_pd_256_2(<4 x double> %a0) #0 {
10281012
define <4 x float> @test_x86_avx_vpermilvar_ps(<4 x float> %a0, <4 x i32> %a1) #0 {
10291013
; CHECK-LABEL: @test_x86_avx_vpermilvar_ps(
10301014
; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 8
1031-
; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 16) to ptr), align 8
10321015
; CHECK-NEXT: call void @llvm.donothing()
1033-
; CHECK-NEXT: [[TMP3:%.*]] = extractelement <4 x i32> [[TMP2]], i64 0
1034-
; CHECK-NEXT: [[TMP15:%.*]] = and i32 [[TMP3]], 3
1035-
; CHECK-NEXT: [[TMP5:%.*]] = or i32 [[TMP3]], [[TMP15]]
1036-
; CHECK-NEXT: [[TMP6:%.*]] = extractelement <4 x i32> [[TMP2]], i64 1
1037-
; CHECK-NEXT: [[TMP7:%.*]] = and i32 [[TMP6]], 3
1038-
; CHECK-NEXT: [[TMP8:%.*]] = or i32 [[TMP6]], [[TMP7]]
1039-
; CHECK-NEXT: [[TMP9:%.*]] = extractelement <4 x i32> [[TMP2]], i64 2
1040-
; CHECK-NEXT: [[TMP10:%.*]] = and i32 [[TMP9]], 3
1041-
; CHECK-NEXT: [[TMP11:%.*]] = or i32 [[TMP9]], [[TMP10]]
1042-
; CHECK-NEXT: [[TMP12:%.*]] = extractelement <4 x i32> [[TMP2]], i64 3
1043-
; CHECK-NEXT: [[TMP13:%.*]] = and i32 [[TMP12]], 3
1044-
; CHECK-NEXT: [[TMP14:%.*]] = or i32 [[TMP12]], [[TMP13]]
1016+
; CHECK-NEXT: [[TMP2:%.*]] = trunc <4 x i32> [[A1:%.*]] to <4 x i2>
10451017
; CHECK-NEXT: [[A0:%.*]] = bitcast <4 x i32> [[TMP1]] to <4 x float>
1046-
; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.x86.avx.vpermilvar.ps(<4 x float> [[A0]], <4 x i32> [[A1:%.*]])
1018+
; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.x86.avx.vpermilvar.ps(<4 x float> [[A0]], <4 x i32> [[A1]])
10471019
; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x float> [[RES]] to <4 x i32>
1048-
; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i32 [[TMP14]], 0
1049-
; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP18:%.*]], label [[TMP19:%.*]], !prof [[PROF1]]
1050-
; CHECK: 18:
1020+
; CHECK-NEXT: [[TMP6:%.*]] = bitcast <4 x i2> [[TMP2]] to i8
1021+
; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i8 [[TMP6]], 0
1022+
; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP7:%.*]], label [[TMP8:%.*]], !prof [[PROF1]]
1023+
; CHECK: 7:
10511024
; CHECK-NEXT: call void @__msan_warning_noreturn()
10521025
; CHECK-NEXT: unreachable
1053-
; CHECK: 19:
1026+
; CHECK: 8:
10541027
; CHECK-NEXT: [[RES1:%.*]] = call <4 x float> @llvm.x86.avx.vpermilvar.ps(<4 x float> [[A2:%.*]], <4 x i32> [[A1]])
10551028
; CHECK-NEXT: store <4 x i32> [[TMP4]], ptr @__msan_retval_tls, align 8
10561029
; CHECK-NEXT: ret <4 x float> [[RES1]]
@@ -1074,27 +1047,17 @@ define <4 x float> @test_x86_avx_vpermilvar_ps_load(<4 x float> %a0, ptr %a1) #0
10741047
; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 87960930222080
10751048
; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr
10761049
; CHECK-NEXT: [[_MSLD:%.*]] = load <4 x i32>, ptr [[TMP7]], align 16
1077-
; CHECK-NEXT: [[TMP8:%.*]] = extractelement <4 x i32> [[_MSLD]], i64 0
1078-
; CHECK-NEXT: [[TMP9:%.*]] = and i32 [[TMP8]], 3
1079-
; CHECK-NEXT: [[TMP20:%.*]] = or i32 [[TMP8]], [[TMP9]]
1080-
; CHECK-NEXT: [[TMP11:%.*]] = extractelement <4 x i32> [[_MSLD]], i64 1
1081-
; CHECK-NEXT: [[TMP12:%.*]] = and i32 [[TMP11]], 3
1082-
; CHECK-NEXT: [[TMP13:%.*]] = or i32 [[TMP11]], [[TMP12]]
1083-
; CHECK-NEXT: [[TMP14:%.*]] = extractelement <4 x i32> [[_MSLD]], i64 2
1084-
; CHECK-NEXT: [[TMP15:%.*]] = and i32 [[TMP14]], 3
1085-
; CHECK-NEXT: [[TMP16:%.*]] = or i32 [[TMP14]], [[TMP15]]
1086-
; CHECK-NEXT: [[TMP17:%.*]] = extractelement <4 x i32> [[_MSLD]], i64 3
1087-
; CHECK-NEXT: [[TMP18:%.*]] = and i32 [[TMP17]], 3
1088-
; CHECK-NEXT: [[TMP19:%.*]] = or i32 [[TMP17]], [[TMP18]]
1050+
; CHECK-NEXT: [[TMP8:%.*]] = trunc <4 x i32> [[A2]] to <4 x i2>
10891051
; CHECK-NEXT: [[A0:%.*]] = bitcast <4 x i32> [[TMP2]] to <4 x float>
10901052
; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.x86.avx.vpermilvar.ps(<4 x float> [[A0]], <4 x i32> [[A2]])
10911053
; CHECK-NEXT: [[TMP10:%.*]] = bitcast <4 x float> [[RES]] to <4 x i32>
1092-
; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i32 [[TMP19]], 0
1093-
; CHECK-NEXT: br i1 [[_MSCMP1]], label [[TMP23:%.*]], label [[TMP24:%.*]], !prof [[PROF1]]
1094-
; CHECK: 23:
1054+
; CHECK-NEXT: [[TMP12:%.*]] = bitcast <4 x i2> [[TMP8]] to i8
1055+
; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i8 [[TMP12]], 0
1056+
; CHECK-NEXT: br i1 [[_MSCMP1]], label [[TMP13:%.*]], label [[TMP14:%.*]], !prof [[PROF1]]
1057+
; CHECK: 13:
10951058
; CHECK-NEXT: call void @__msan_warning_noreturn()
10961059
; CHECK-NEXT: unreachable
1097-
; CHECK: 24:
1060+
; CHECK: 14:
10981061
; CHECK-NEXT: [[RES1:%.*]] = call <4 x float> @llvm.x86.avx.vpermilvar.ps(<4 x float> [[A3:%.*]], <4 x i32> [[A2]])
10991062
; CHECK-NEXT: store <4 x i32> [[TMP10]], ptr @__msan_retval_tls, align 8
11001063
; CHECK-NEXT: ret <4 x float> [[RES1]]
@@ -1109,41 +1072,18 @@ declare <4 x float> @llvm.x86.avx.vpermilvar.ps(<4 x float>, <4 x i32>) nounwind
11091072
define <8 x float> @test_x86_avx_vpermilvar_ps_256(<8 x float> %a0, <8 x i32> %a1) #0 {
11101073
; CHECK-LABEL: @test_x86_avx_vpermilvar_ps_256(
11111074
; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i32>, ptr @__msan_param_tls, align 8
1112-
; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i32>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 32) to ptr), align 8
11131075
; CHECK-NEXT: call void @llvm.donothing()
1114-
; CHECK-NEXT: [[TMP3:%.*]] = extractelement <8 x i32> [[TMP2]], i64 0
1115-
; CHECK-NEXT: [[TMP27:%.*]] = and i32 [[TMP3]], 7
1116-
; CHECK-NEXT: [[TMP5:%.*]] = or i32 [[TMP3]], [[TMP27]]
1117-
; CHECK-NEXT: [[TMP6:%.*]] = extractelement <8 x i32> [[TMP2]], i64 1
1118-
; CHECK-NEXT: [[TMP7:%.*]] = and i32 [[TMP6]], 7
1119-
; CHECK-NEXT: [[TMP8:%.*]] = or i32 [[TMP6]], [[TMP7]]
1120-
; CHECK-NEXT: [[TMP9:%.*]] = extractelement <8 x i32> [[TMP2]], i64 2
1121-
; CHECK-NEXT: [[TMP10:%.*]] = and i32 [[TMP9]], 7
1122-
; CHECK-NEXT: [[TMP11:%.*]] = or i32 [[TMP9]], [[TMP10]]
1123-
; CHECK-NEXT: [[TMP12:%.*]] = extractelement <8 x i32> [[TMP2]], i64 3
1124-
; CHECK-NEXT: [[TMP13:%.*]] = and i32 [[TMP12]], 7
1125-
; CHECK-NEXT: [[TMP14:%.*]] = or i32 [[TMP12]], [[TMP13]]
1126-
; CHECK-NEXT: [[TMP15:%.*]] = extractelement <8 x i32> [[TMP2]], i64 4
1127-
; CHECK-NEXT: [[TMP16:%.*]] = and i32 [[TMP15]], 7
1128-
; CHECK-NEXT: [[TMP17:%.*]] = or i32 [[TMP15]], [[TMP16]]
1129-
; CHECK-NEXT: [[TMP18:%.*]] = extractelement <8 x i32> [[TMP2]], i64 5
1130-
; CHECK-NEXT: [[TMP19:%.*]] = and i32 [[TMP18]], 7
1131-
; CHECK-NEXT: [[TMP20:%.*]] = or i32 [[TMP18]], [[TMP19]]
1132-
; CHECK-NEXT: [[TMP21:%.*]] = extractelement <8 x i32> [[TMP2]], i64 6
1133-
; CHECK-NEXT: [[TMP22:%.*]] = and i32 [[TMP21]], 7
1134-
; CHECK-NEXT: [[TMP23:%.*]] = or i32 [[TMP21]], [[TMP22]]
1135-
; CHECK-NEXT: [[TMP24:%.*]] = extractelement <8 x i32> [[TMP2]], i64 7
1136-
; CHECK-NEXT: [[TMP25:%.*]] = and i32 [[TMP24]], 7
1137-
; CHECK-NEXT: [[TMP26:%.*]] = or i32 [[TMP24]], [[TMP25]]
1076+
; CHECK-NEXT: [[TMP2:%.*]] = trunc <8 x i32> [[A1:%.*]] to <8 x i3>
11381077
; CHECK-NEXT: [[A0:%.*]] = bitcast <8 x i32> [[TMP1]] to <8 x float>
1139-
; CHECK-NEXT: [[RES:%.*]] = call <8 x float> @llvm.x86.avx.vpermilvar.ps.256(<8 x float> [[A0]], <8 x i32> [[A1:%.*]])
1078+
; CHECK-NEXT: [[RES:%.*]] = call <8 x float> @llvm.x86.avx.vpermilvar.ps.256(<8 x float> [[A0]], <8 x i32> [[A1]])
11401079
; CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x float> [[RES]] to <8 x i32>
1141-
; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i32 [[TMP26]], 0
1142-
; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP30:%.*]], label [[TMP31:%.*]], !prof [[PROF1]]
1143-
; CHECK: 30:
1080+
; CHECK-NEXT: [[TMP6:%.*]] = bitcast <8 x i3> [[TMP2]] to i24
1081+
; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i24 [[TMP6]], 0
1082+
; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP7:%.*]], label [[TMP8:%.*]], !prof [[PROF1]]
1083+
; CHECK: 7:
11441084
; CHECK-NEXT: call void @__msan_warning_noreturn()
11451085
; CHECK-NEXT: unreachable
1146-
; CHECK: 31:
1086+
; CHECK: 8:
11471087
; CHECK-NEXT: [[RES1:%.*]] = call <8 x float> @llvm.x86.avx.vpermilvar.ps.256(<8 x float> [[A2:%.*]], <8 x i32> [[A1]])
11481088
; CHECK-NEXT: store <8 x i32> [[TMP4]], ptr @__msan_retval_tls, align 8
11491089
; CHECK-NEXT: ret <8 x float> [[RES1]]

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