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[RISCV] Use a precise size for MMO on scalable spill and fill (#133171)
The primary effect of this is that we get proper scalable sizes printed by the assembler, but this may also enable proper aliasing analysis. I don't see any test changes resulting from the later. Getting the size is slightly tricky as we store the scalable size as a non-scalable quantity in the object size field for the frame index. We really should remove that hack at some point... For the synthetic tuple spills and fills, I dropped the size from the split loads and stores to avoid incorrect (overly large) sizes. We could also divide by the NF factor if we felt like writing the code to do so.
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‎llvm/lib/CodeGen/MachineInstr.cpp

Lines changed: 8 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -2525,18 +2525,23 @@ using MMOList = SmallVector<const MachineMemOperand *, 2>;
25252525

25262526
static LocationSize getSpillSlotSize(const MMOList &Accesses,
25272527
const MachineFrameInfo &MFI) {
2528-
uint64_t Size = 0;
2528+
std::optional<TypeSize> Size;
25292529
for (const auto *A : Accesses) {
25302530
if (MFI.isSpillSlotObjectIndex(
25312531
cast<FixedStackPseudoSourceValue>(A->getPseudoValue())
25322532
->getFrameIndex())) {
25332533
LocationSize S = A->getSize();
25342534
if (!S.hasValue())
25352535
return LocationSize::beforeOrAfterPointer();
2536-
Size += S.getValue();
2536+
if (!Size)
2537+
Size = S.getValue();
2538+
else
2539+
Size = *Size + S.getValue();
25372540
}
25382541
}
2539-
return Size;
2542+
if (!Size)
2543+
return LocationSize::precise(0);
2544+
return LocationSize::precise(*Size);
25402545
}
25412546

25422547
std::optional<LocationSize>

‎llvm/lib/Target/RISCV/RISCVInstrInfo.cpp

Lines changed: 6 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -705,9 +705,11 @@ void RISCVInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
705705
llvm_unreachable("Can't store this register to stack slot");
706706

707707
if (IsScalableVector) {
708+
LocationSize LocSize =
709+
LocationSize::precise(TypeSize::getScalable(MFI.getObjectSize(FI)));
708710
MachineMemOperand *MMO = MF->getMachineMemOperand(
709711
MachinePointerInfo::getFixedStack(*MF, FI), MachineMemOperand::MOStore,
710-
LocationSize::beforeOrAfterPointer(), MFI.getObjectAlign(FI));
712+
LocSize, MFI.getObjectAlign(FI));
711713

712714
MFI.setStackID(FI, TargetStackID::ScalableVector);
713715
BuildMI(MBB, I, DebugLoc(), get(Opcode))
@@ -797,9 +799,11 @@ void RISCVInstrInfo::loadRegFromStackSlot(
797799
llvm_unreachable("Can't load this register from stack slot");
798800

799801
if (IsScalableVector) {
802+
LocationSize LocSize =
803+
LocationSize::precise(TypeSize::getScalable(MFI.getObjectSize(FI)));
800804
MachineMemOperand *MMO = MF->getMachineMemOperand(
801805
MachinePointerInfo::getFixedStack(*MF, FI), MachineMemOperand::MOLoad,
802-
LocationSize::beforeOrAfterPointer(), MFI.getObjectAlign(FI));
806+
LocSize, MFI.getObjectAlign(FI));
803807

804808
MFI.setStackID(FI, TargetStackID::ScalableVector);
805809
BuildMI(MBB, I, DL, get(Opcode), DstReg)

‎llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp

Lines changed: 9 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -406,6 +406,10 @@ void RISCVRegisterInfo::lowerVSPILL(MachineBasicBlock::iterator II) const {
406406
Register Base = II->getOperand(1).getReg();
407407
bool IsBaseKill = II->getOperand(1).isKill();
408408
Register NewBase = MRI.createVirtualRegister(&RISCV::GPRRegClass);
409+
410+
auto *OldMMO = *(II->memoperands_begin());
411+
auto *NewMMO = MF.getMachineMemOperand(OldMMO, OldMMO->getOffset(),
412+
LocationSize::beforeOrAfterPointer());
409413
for (unsigned I = 0; I < NF; ++I) {
410414
// Adding implicit-use of super register to describe we are using part of
411415
// super register, that prevents machine verifier complaining when part of
@@ -414,7 +418,7 @@ void RISCVRegisterInfo::lowerVSPILL(MachineBasicBlock::iterator II) const {
414418
BuildMI(MBB, II, DL, TII->get(Opcode))
415419
.addReg(TRI->getSubReg(SrcReg, SubRegIdx + I))
416420
.addReg(Base, getKillRegState(I == NF - 1))
417-
.addMemOperand(*(II->memoperands_begin()))
421+
.addMemOperand(NewMMO)
418422
.addReg(SrcReg, RegState::Implicit);
419423
if (I != NF - 1)
420424
BuildMI(MBB, II, DL, TII->get(RISCV::ADD), NewBase)
@@ -483,11 +487,14 @@ void RISCVRegisterInfo::lowerVRELOAD(MachineBasicBlock::iterator II) const {
483487
Register Base = II->getOperand(1).getReg();
484488
bool IsBaseKill = II->getOperand(1).isKill();
485489
Register NewBase = MRI.createVirtualRegister(&RISCV::GPRRegClass);
490+
auto *OldMMO = *(II->memoperands_begin());
491+
auto *NewMMO = MF.getMachineMemOperand(OldMMO, OldMMO->getOffset(),
492+
LocationSize::beforeOrAfterPointer());
486493
for (unsigned I = 0; I < NF; ++I) {
487494
BuildMI(MBB, II, DL, TII->get(Opcode),
488495
TRI->getSubReg(DestReg, SubRegIdx + I))
489496
.addReg(Base, getKillRegState(I == NF - 1))
490-
.addMemOperand(*(II->memoperands_begin()));
497+
.addMemOperand(NewMMO);
491498
if (I != NF - 1)
492499
BuildMI(MBB, II, DL, TII->get(RISCV::ADD), NewBase)
493500
.addReg(Base, getKillRegState(I != 0 || IsBaseKill))

‎llvm/test/CodeGen/RISCV/early-clobber-tied-def-subreg-liveness.ll

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -32,7 +32,7 @@ define void @_Z3foov() {
3232
; CHECK-NEXT: slli a0, a0, 3
3333
; CHECK-NEXT: add a0, sp, a0
3434
; CHECK-NEXT: addi a0, a0, 16
35-
; CHECK-NEXT: vs1r.v v10, (a0) # Unknown-size Folded Spill
35+
; CHECK-NEXT: vs1r.v v10, (a0) # vscale x 8-byte Folded Spill
3636
; CHECK-NEXT: lui a0, %hi(.L__const._Z3foov.var_46)
3737
; CHECK-NEXT: addi a0, a0, %lo(.L__const._Z3foov.var_46)
3838
; CHECK-NEXT: vle16.v v10, (a0)
@@ -72,7 +72,7 @@ define void @_Z3foov() {
7272
; CHECK-NEXT: slli a0, a0, 3
7373
; CHECK-NEXT: add a0, sp, a0
7474
; CHECK-NEXT: addi a0, a0, 16
75-
; CHECK-NEXT: vl1r.v v14, (a0) # Unknown-size Folded Reload
75+
; CHECK-NEXT: vl1r.v v14, (a0) # vscale x 8-byte Folded Reload
7676
; CHECK-NEXT: vsetvli zero, zero, e16, m2, tu, mu
7777
; CHECK-NEXT: vsext.vf2 v8, v14, v0.t
7878
; CHECK-NEXT: lui a0, %hi(.L__const._Z3foov.var_44)

‎llvm/test/CodeGen/RISCV/intrinsic-cttz-elts-vscale.ll

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -64,7 +64,7 @@ define i64 @ctz_nxv8i1_no_range(<vscale x 8 x i16> %a) {
6464
; RV32-NEXT: sub sp, sp, a0
6565
; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x30, 0x22, 0x11, 0x02, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 48 + 2 * vlenb
6666
; RV32-NEXT: addi a0, sp, 32
67-
; RV32-NEXT: vs2r.v v8, (a0) # Unknown-size Folded Spill
67+
; RV32-NEXT: vs2r.v v8, (a0) # vscale x 16-byte Folded Spill
6868
; RV32-NEXT: csrr a0, vlenb
6969
; RV32-NEXT: srli a0, a0, 3
7070
; RV32-NEXT: li a2, 8
@@ -79,7 +79,7 @@ define i64 @ctz_nxv8i1_no_range(<vscale x 8 x i16> %a) {
7979
; RV32-NEXT: vid.v v8
8080
; RV32-NEXT: li a2, -1
8181
; RV32-NEXT: addi a3, sp, 32
82-
; RV32-NEXT: vl2r.v v24, (a3) # Unknown-size Folded Reload
82+
; RV32-NEXT: vl2r.v v24, (a3) # vscale x 16-byte Folded Reload
8383
; RV32-NEXT: vsetvli zero, zero, e16, m2, ta, ma
8484
; RV32-NEXT: vmsne.vi v0, v24, 0
8585
; RV32-NEXT: vsetvli zero, zero, e64, m8, ta, ma

‎llvm/test/CodeGen/RISCV/pr69586.ll

Lines changed: 28 additions & 28 deletions
Original file line numberDiff line numberDiff line change
@@ -102,7 +102,7 @@ define void @test(ptr %0, ptr %1, i64 %2) {
102102
; NOREMAT-NEXT: sf.vc.vv 3, 0, v8, v10
103103
; NOREMAT-NEXT: vle32.v v8, (a4)
104104
; NOREMAT-NEXT: addi a0, sp, 640
105-
; NOREMAT-NEXT: vs2r.v v8, (a0) # Unknown-size Folded Spill
105+
; NOREMAT-NEXT: vs2r.v v8, (a0) # vscale x 16-byte Folded Spill
106106
; NOREMAT-NEXT: add a4, a7, t4
107107
; NOREMAT-NEXT: vle32.v v10, (a4)
108108
; NOREMAT-NEXT: sf.vc.vv 3, 0, v2, v0
@@ -377,7 +377,7 @@ define void @test(ptr %0, ptr %1, i64 %2) {
377377
; NOREMAT-NEXT: vle32.v v14, (a2)
378378
; NOREMAT-NEXT: vle32.v v30, (a2)
379379
; NOREMAT-NEXT: addi a0, sp, 640
380-
; NOREMAT-NEXT: vl2r.v v12, (a0) # Unknown-size Folded Reload
380+
; NOREMAT-NEXT: vl2r.v v12, (a0) # vscale x 16-byte Folded Reload
381381
; NOREMAT-NEXT: sf.vc.vv 3, 0, v12, v22
382382
; NOREMAT-NEXT: addiw a2, s0, -512
383383
; NOREMAT-NEXT: sd a2, 336(sp) # 8-byte Folded Spill
@@ -998,7 +998,7 @@ define void @test(ptr %0, ptr %1, i64 %2) {
998998
; REMAT-NEXT: slli a2, a2, 4
999999
; REMAT-NEXT: add a2, sp, a2
10001000
; REMAT-NEXT: addi a2, a2, 432
1001-
; REMAT-NEXT: vs2r.v v6, (a2) # Unknown-size Folded Spill
1001+
; REMAT-NEXT: vs2r.v v6, (a2) # vscale x 16-byte Folded Spill
10021002
; REMAT-NEXT: add a2, a0, t2
10031003
; REMAT-NEXT: vle32.v v4, (a0)
10041004
; REMAT-NEXT: vle32.v v2, (a2)
@@ -1008,7 +1008,7 @@ define void @test(ptr %0, ptr %1, i64 %2) {
10081008
; REMAT-NEXT: mul a2, a2, a5
10091009
; REMAT-NEXT: add a2, sp, a2
10101010
; REMAT-NEXT: addi a2, a2, 432
1011-
; REMAT-NEXT: vs2r.v v6, (a2) # Unknown-size Folded Spill
1011+
; REMAT-NEXT: vs2r.v v6, (a2) # vscale x 16-byte Folded Spill
10121012
; REMAT-NEXT: add a2, a0, t3
10131013
; REMAT-NEXT: sf.vc.vv 3, 0, v4, v8
10141014
; REMAT-NEXT: vle32.v v4, (a2)
@@ -1027,7 +1027,7 @@ define void @test(ptr %0, ptr %1, i64 %2) {
10271027
; REMAT-NEXT: mul a2, a2, a5
10281028
; REMAT-NEXT: add a2, sp, a2
10291029
; REMAT-NEXT: addi a2, a2, 432
1030-
; REMAT-NEXT: vs2r.v v8, (a2) # Unknown-size Folded Spill
1030+
; REMAT-NEXT: vs2r.v v8, (a2) # vscale x 16-byte Folded Spill
10311031
; REMAT-NEXT: add a2, a0, t6
10321032
; REMAT-NEXT: vle32.v v18, (a2)
10331033
; REMAT-NEXT: sf.vc.vv 3, 0, v20, v22
@@ -1046,7 +1046,7 @@ define void @test(ptr %0, ptr %1, i64 %2) {
10461046
; REMAT-NEXT: slli a5, a5, 4
10471047
; REMAT-NEXT: add a5, sp, a5
10481048
; REMAT-NEXT: addi a5, a5, 432
1049-
; REMAT-NEXT: vl2r.v v12, (a5) # Unknown-size Folded Reload
1049+
; REMAT-NEXT: vl2r.v v12, (a5) # vscale x 16-byte Folded Reload
10501050
; REMAT-NEXT: sf.vc.vv 3, 0, v12, v2
10511051
; REMAT-NEXT: vle32.v v2, (a2)
10521052
; REMAT-NEXT: add a2, a0, s3
@@ -1056,7 +1056,7 @@ define void @test(ptr %0, ptr %1, i64 %2) {
10561056
; REMAT-NEXT: mul a5, a5, a6
10571057
; REMAT-NEXT: add a5, sp, a5
10581058
; REMAT-NEXT: addi a5, a5, 432
1059-
; REMAT-NEXT: vl2r.v v16, (a5) # Unknown-size Folded Reload
1059+
; REMAT-NEXT: vl2r.v v16, (a5) # vscale x 16-byte Folded Reload
10601060
; REMAT-NEXT: sf.vc.vv 3, 0, v16, v4
10611061
; REMAT-NEXT: vle32.v v30, (a2)
10621062
; REMAT-NEXT: add a2, a0, s4
@@ -1074,7 +1074,7 @@ define void @test(ptr %0, ptr %1, i64 %2) {
10741074
; REMAT-NEXT: mul a5, a5, a6
10751075
; REMAT-NEXT: add a5, sp, a5
10761076
; REMAT-NEXT: addi a5, a5, 432
1077-
; REMAT-NEXT: vl2r.v v0, (a5) # Unknown-size Folded Reload
1077+
; REMAT-NEXT: vl2r.v v0, (a5) # vscale x 16-byte Folded Reload
10781078
; REMAT-NEXT: sf.vc.vv 3, 0, v0, v18
10791079
; REMAT-NEXT: vle32.v v0, (a2)
10801080
; REMAT-NEXT: add a2, a0, s7
@@ -1097,7 +1097,7 @@ define void @test(ptr %0, ptr %1, i64 %2) {
10971097
; REMAT-NEXT: slli a2, a2, 3
10981098
; REMAT-NEXT: add a2, sp, a2
10991099
; REMAT-NEXT: addi a2, a2, 432
1100-
; REMAT-NEXT: vs2r.v v12, (a2) # Unknown-size Folded Spill
1100+
; REMAT-NEXT: vs2r.v v12, (a2) # vscale x 16-byte Folded Spill
11011101
; REMAT-NEXT: add a2, a0, s11
11021102
; REMAT-NEXT: vle32.v v12, (a2)
11031103
; REMAT-NEXT: sf.vc.vv 3, 0, v30, v16
@@ -1110,7 +1110,7 @@ define void @test(ptr %0, ptr %1, i64 %2) {
11101110
; REMAT-NEXT: slli a2, a2, 1
11111111
; REMAT-NEXT: add a2, sp, a2
11121112
; REMAT-NEXT: addi a2, a2, 432
1113-
; REMAT-NEXT: vs2r.v v10, (a2) # Unknown-size Folded Spill
1113+
; REMAT-NEXT: vs2r.v v10, (a2) # vscale x 16-byte Folded Spill
11141114
; REMAT-NEXT: add a2, a0, a4
11151115
; REMAT-NEXT: vle32.v v10, (a2)
11161116
; REMAT-NEXT: sf.vc.vv 3, 0, v4, v14
@@ -1119,7 +1119,7 @@ define void @test(ptr %0, ptr %1, i64 %2) {
11191119
; REMAT-NEXT: slli a2, a2, 2
11201120
; REMAT-NEXT: add a2, sp, a2
11211121
; REMAT-NEXT: addi a2, a2, 432
1122-
; REMAT-NEXT: vs2r.v v14, (a2) # Unknown-size Folded Spill
1122+
; REMAT-NEXT: vs2r.v v14, (a2) # vscale x 16-byte Folded Spill
11231123
; REMAT-NEXT: add a2, a0, a3
11241124
; REMAT-NEXT: vle32.v v14, (a2)
11251125
; REMAT-NEXT: sf.vc.vv 3, 0, v0, v18
@@ -1128,21 +1128,21 @@ define void @test(ptr %0, ptr %1, i64 %2) {
11281128
; REMAT-NEXT: slli a2, a2, 4
11291129
; REMAT-NEXT: add a2, sp, a2
11301130
; REMAT-NEXT: addi a2, a2, 432
1131-
; REMAT-NEXT: vs2r.v v18, (a2) # Unknown-size Folded Spill
1131+
; REMAT-NEXT: vs2r.v v18, (a2) # vscale x 16-byte Folded Spill
11321132
; REMAT-NEXT: li a5, 7
11331133
; REMAT-NEXT: slli a5, a5, 11
11341134
; REMAT-NEXT: add a2, a0, a5
11351135
; REMAT-NEXT: vle32.v v18, (a2)
11361136
; REMAT-NEXT: addi a3, sp, 432
1137-
; REMAT-NEXT: vs2r.v v18, (a3) # Unknown-size Folded Spill
1137+
; REMAT-NEXT: vs2r.v v18, (a3) # vscale x 16-byte Folded Spill
11381138
; REMAT-NEXT: sf.vc.vv 3, 0, v22, v20
11391139
; REMAT-NEXT: vle32.v v18, (a2)
11401140
; REMAT-NEXT: csrr a2, vlenb
11411141
; REMAT-NEXT: li a3, 14
11421142
; REMAT-NEXT: mul a2, a2, a3
11431143
; REMAT-NEXT: add a2, sp, a2
11441144
; REMAT-NEXT: addi a2, a2, 432
1145-
; REMAT-NEXT: vs2r.v v18, (a2) # Unknown-size Folded Spill
1145+
; REMAT-NEXT: vs2r.v v18, (a2) # vscale x 16-byte Folded Spill
11461146
; REMAT-NEXT: li a2, 29
11471147
; REMAT-NEXT: slli a2, a2, 9
11481148
; REMAT-NEXT: add a2, a0, a2
@@ -1154,7 +1154,7 @@ define void @test(ptr %0, ptr %1, i64 %2) {
11541154
; REMAT-NEXT: mul a2, a2, a3
11551155
; REMAT-NEXT: add a2, sp, a2
11561156
; REMAT-NEXT: addi a2, a2, 432
1157-
; REMAT-NEXT: vs2r.v v20, (a2) # Unknown-size Folded Spill
1157+
; REMAT-NEXT: vs2r.v v20, (a2) # vscale x 16-byte Folded Spill
11581158
; REMAT-NEXT: li a2, 15
11591159
; REMAT-NEXT: slli a2, a2, 10
11601160
; REMAT-NEXT: add a2, a0, a2
@@ -1166,7 +1166,7 @@ define void @test(ptr %0, ptr %1, i64 %2) {
11661166
; REMAT-NEXT: mul a2, a2, a3
11671167
; REMAT-NEXT: add a2, sp, a2
11681168
; REMAT-NEXT: addi a2, a2, 432
1169-
; REMAT-NEXT: vs2r.v v8, (a2) # Unknown-size Folded Spill
1169+
; REMAT-NEXT: vs2r.v v8, (a2) # vscale x 16-byte Folded Spill
11701170
; REMAT-NEXT: li a2, 31
11711171
; REMAT-NEXT: slli a2, a2, 9
11721172
; REMAT-NEXT: add a2, a0, a2
@@ -1175,14 +1175,14 @@ define void @test(ptr %0, ptr %1, i64 %2) {
11751175
; REMAT-NEXT: slli a3, a3, 3
11761176
; REMAT-NEXT: add a3, sp, a3
11771177
; REMAT-NEXT: addi a3, a3, 432
1178-
; REMAT-NEXT: vl2r.v v8, (a3) # Unknown-size Folded Reload
1178+
; REMAT-NEXT: vl2r.v v8, (a3) # vscale x 16-byte Folded Reload
11791179
; REMAT-NEXT: sf.vc.vv 3, 0, v8, v12
11801180
; REMAT-NEXT: vle32.v v8, (a2)
11811181
; REMAT-NEXT: csrr a2, vlenb
11821182
; REMAT-NEXT: slli a2, a2, 3
11831183
; REMAT-NEXT: add a2, sp, a2
11841184
; REMAT-NEXT: addi a2, a2, 432
1185-
; REMAT-NEXT: vs2r.v v8, (a2) # Unknown-size Folded Spill
1185+
; REMAT-NEXT: vs2r.v v8, (a2) # vscale x 16-byte Folded Spill
11861186
; REMAT-NEXT: lui a2, 4
11871187
; REMAT-NEXT: add a2, a0, a2
11881188
; REMAT-NEXT: vle32.v v4, (a2)
@@ -1193,7 +1193,7 @@ define void @test(ptr %0, ptr %1, i64 %2) {
11931193
; REMAT-NEXT: mul a2, a2, a3
11941194
; REMAT-NEXT: add a2, sp, a2
11951195
; REMAT-NEXT: addi a2, a2, 432
1196-
; REMAT-NEXT: vs2r.v v8, (a2) # Unknown-size Folded Spill
1196+
; REMAT-NEXT: vs2r.v v8, (a2) # vscale x 16-byte Folded Spill
11971197
; REMAT-NEXT: lui a2, 4
11981198
; REMAT-NEXT: addiw a2, a2, 512
11991199
; REMAT-NEXT: add a2, a0, a2
@@ -1202,7 +1202,7 @@ define void @test(ptr %0, ptr %1, i64 %2) {
12021202
; REMAT-NEXT: slli a3, a3, 1
12031203
; REMAT-NEXT: add a3, sp, a3
12041204
; REMAT-NEXT: addi a3, a3, 432
1205-
; REMAT-NEXT: vl2r.v v8, (a3) # Unknown-size Folded Reload
1205+
; REMAT-NEXT: vl2r.v v8, (a3) # vscale x 16-byte Folded Reload
12061206
; REMAT-NEXT: sf.vc.vv 3, 0, v8, v10
12071207
; REMAT-NEXT: vle32.v v20, (a2)
12081208
; REMAT-NEXT: li a2, 17
@@ -1213,7 +1213,7 @@ define void @test(ptr %0, ptr %1, i64 %2) {
12131213
; REMAT-NEXT: slli a3, a3, 2
12141214
; REMAT-NEXT: add a3, sp, a3
12151215
; REMAT-NEXT: addi a3, a3, 432
1216-
; REMAT-NEXT: vl2r.v v8, (a3) # Unknown-size Folded Reload
1216+
; REMAT-NEXT: vl2r.v v8, (a3) # vscale x 16-byte Folded Reload
12171217
; REMAT-NEXT: sf.vc.vv 3, 0, v8, v14
12181218
; REMAT-NEXT: vle32.v v22, (a2)
12191219
; REMAT-NEXT: lui a2, 4
@@ -1224,9 +1224,9 @@ define void @test(ptr %0, ptr %1, i64 %2) {
12241224
; REMAT-NEXT: slli a3, a3, 4
12251225
; REMAT-NEXT: add a3, sp, a3
12261226
; REMAT-NEXT: addi a3, a3, 432
1227-
; REMAT-NEXT: vl2r.v v8, (a3) # Unknown-size Folded Reload
1227+
; REMAT-NEXT: vl2r.v v8, (a3) # vscale x 16-byte Folded Reload
12281228
; REMAT-NEXT: addi a3, sp, 432
1229-
; REMAT-NEXT: vl2r.v v10, (a3) # Unknown-size Folded Reload
1229+
; REMAT-NEXT: vl2r.v v10, (a3) # vscale x 16-byte Folded Reload
12301230
; REMAT-NEXT: sf.vc.vv 3, 0, v8, v10
12311231
; REMAT-NEXT: vle32.v v8, (a2)
12321232
; REMAT-NEXT: li a2, 9
@@ -1238,7 +1238,7 @@ define void @test(ptr %0, ptr %1, i64 %2) {
12381238
; REMAT-NEXT: mul a3, a3, a4
12391239
; REMAT-NEXT: add a3, sp, a3
12401240
; REMAT-NEXT: addi a3, a3, 432
1241-
; REMAT-NEXT: vl2r.v v10, (a3) # Unknown-size Folded Reload
1241+
; REMAT-NEXT: vl2r.v v10, (a3) # vscale x 16-byte Folded Reload
12421242
; REMAT-NEXT: sf.vc.vv 3, 0, v10, v18
12431243
; REMAT-NEXT: vle32.v v10, (a2)
12441244
; REMAT-NEXT: lui a2, 5
@@ -1250,7 +1250,7 @@ define void @test(ptr %0, ptr %1, i64 %2) {
12501250
; REMAT-NEXT: mul a3, a3, a4
12511251
; REMAT-NEXT: add a3, sp, a3
12521252
; REMAT-NEXT: addi a3, a3, 432
1253-
; REMAT-NEXT: vl2r.v v12, (a3) # Unknown-size Folded Reload
1253+
; REMAT-NEXT: vl2r.v v12, (a3) # vscale x 16-byte Folded Reload
12541254
; REMAT-NEXT: sf.vc.vv 3, 0, v12, v30
12551255
; REMAT-NEXT: vle32.v v12, (a2)
12561256
; REMAT-NEXT: li a2, 19
@@ -1262,7 +1262,7 @@ define void @test(ptr %0, ptr %1, i64 %2) {
12621262
; REMAT-NEXT: mul a3, a3, a4
12631263
; REMAT-NEXT: add a3, sp, a3
12641264
; REMAT-NEXT: addi a3, a3, 432
1265-
; REMAT-NEXT: vl2r.v v14, (a3) # Unknown-size Folded Reload
1265+
; REMAT-NEXT: vl2r.v v14, (a3) # vscale x 16-byte Folded Reload
12661266
; REMAT-NEXT: sf.vc.vv 3, 0, v14, v6
12671267
; REMAT-NEXT: vle32.v v14, (a2)
12681268
; REMAT-NEXT: lui a2, 5
@@ -1273,7 +1273,7 @@ define void @test(ptr %0, ptr %1, i64 %2) {
12731273
; REMAT-NEXT: slli a3, a3, 3
12741274
; REMAT-NEXT: add a3, sp, a3
12751275
; REMAT-NEXT: addi a3, a3, 432
1276-
; REMAT-NEXT: vl2r.v v16, (a3) # Unknown-size Folded Reload
1276+
; REMAT-NEXT: vl2r.v v16, (a3) # vscale x 16-byte Folded Reload
12771277
; REMAT-NEXT: sf.vc.vv 3, 0, v16, v4
12781278
; REMAT-NEXT: vle32.v v16, (a2)
12791279
; REMAT-NEXT: lui a2, 5
@@ -1284,7 +1284,7 @@ define void @test(ptr %0, ptr %1, i64 %2) {
12841284
; REMAT-NEXT: mul a3, a3, a4
12851285
; REMAT-NEXT: add a3, sp, a3
12861286
; REMAT-NEXT: addi a3, a3, 432
1287-
; REMAT-NEXT: vl2r.v v18, (a3) # Unknown-size Folded Reload
1287+
; REMAT-NEXT: vl2r.v v18, (a3) # vscale x 16-byte Folded Reload
12881288
; REMAT-NEXT: sf.vc.vv 3, 0, v18, v2
12891289
; REMAT-NEXT: vle32.v v18, (a2)
12901290
; REMAT-NEXT: lui a2, 5

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