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[RISCV] Add missing indexed load/store intrinsic tests for zvfbfmin (#148097)
riscv-non-isa/rvv-intrinsic-doc@d6d33a0 adds missing indexed load/store which with other index size.
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‎clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei32.c

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// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4
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// REQUIRES: riscv-registered-target
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// RUN: %clang_cc1 -triple riscv64 -target-feature +zve64x \
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// RUN: -target-feature +zvfbfmin -disable-O0-optnone \
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// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
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// RUN: FileCheck --check-prefix=CHECK-RV64 %s
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#include <riscv_vector.h>
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// CHECK-RV64-LABEL: define dso_local <vscale x 1 x bfloat> @test_vloxei32_v_bf16mf4(
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// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], <vscale x 1 x i32> [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
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// CHECK-RV64-NEXT: entry:
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// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x bfloat> @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat> poison, ptr [[RS1]], <vscale x 1 x i32> [[RS2]], i64 [[VL]])
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// CHECK-RV64-NEXT: ret <vscale x 1 x bfloat> [[TMP0]]
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//
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vbfloat16mf4_t test_vloxei32_v_bf16mf4(const __bf16 *rs1, vuint32mf2_t rs2,
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size_t vl) {
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return __riscv_vloxei32_v_bf16mf4(rs1, rs2, vl);
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}
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// CHECK-RV64-LABEL: define dso_local <vscale x 2 x bfloat> @test_vloxei32_v_bf16mf2(
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// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], <vscale x 2 x i32> [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
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// CHECK-RV64-NEXT: entry:
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// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x bfloat> @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat> poison, ptr [[RS1]], <vscale x 2 x i32> [[RS2]], i64 [[VL]])
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// CHECK-RV64-NEXT: ret <vscale x 2 x bfloat> [[TMP0]]
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//
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vbfloat16mf2_t test_vloxei32_v_bf16mf2(const __bf16 *rs1, vuint32m1_t rs2,
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size_t vl) {
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return __riscv_vloxei32_v_bf16mf2(rs1, rs2, vl);
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}
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// CHECK-RV64-LABEL: define dso_local <vscale x 4 x bfloat> @test_vloxei32_v_bf16m1(
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// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], <vscale x 4 x i32> [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
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// CHECK-RV64-NEXT: entry:
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// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x bfloat> @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat> poison, ptr [[RS1]], <vscale x 4 x i32> [[RS2]], i64 [[VL]])
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// CHECK-RV64-NEXT: ret <vscale x 4 x bfloat> [[TMP0]]
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//
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vbfloat16m1_t test_vloxei32_v_bf16m1(const __bf16 *rs1, vuint32m2_t rs2,
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size_t vl) {
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return __riscv_vloxei32_v_bf16m1(rs1, rs2, vl);
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}
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// CHECK-RV64-LABEL: define dso_local <vscale x 8 x bfloat> @test_vloxei32_v_bf16m2(
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// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], <vscale x 8 x i32> [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
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// CHECK-RV64-NEXT: entry:
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// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x bfloat> @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i32.i64(<vscale x 8 x bfloat> poison, ptr [[RS1]], <vscale x 8 x i32> [[RS2]], i64 [[VL]])
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// CHECK-RV64-NEXT: ret <vscale x 8 x bfloat> [[TMP0]]
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//
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vbfloat16m2_t test_vloxei32_v_bf16m2(const __bf16 *rs1, vuint32m4_t rs2,
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size_t vl) {
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return __riscv_vloxei32_v_bf16m2(rs1, rs2, vl);
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}
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// CHECK-RV64-LABEL: define dso_local <vscale x 16 x bfloat> @test_vloxei32_v_bf16m4(
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// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], <vscale x 16 x i32> [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
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// CHECK-RV64-NEXT: entry:
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// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x bfloat> @llvm.riscv.vloxei.nxv16bf16.p0.nxv16i32.i64(<vscale x 16 x bfloat> poison, ptr [[RS1]], <vscale x 16 x i32> [[RS2]], i64 [[VL]])
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// CHECK-RV64-NEXT: ret <vscale x 16 x bfloat> [[TMP0]]
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//
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vbfloat16m4_t test_vloxei32_v_bf16m4(const __bf16 *rs1, vuint32m8_t rs2,
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size_t vl) {
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return __riscv_vloxei32_v_bf16m4(rs1, rs2, vl);
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}
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// CHECK-RV64-LABEL: define dso_local <vscale x 1 x bfloat> @test_vloxei32_v_bf16mf4_m(
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// CHECK-RV64-SAME: <vscale x 1 x i1> [[VM:%.*]], ptr noundef [[RS1:%.*]], <vscale x 1 x i32> [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
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// CHECK-RV64-NEXT: entry:
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// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x bfloat> @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat> poison, ptr [[RS1]], <vscale x 1 x i32> [[RS2]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 3)
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// CHECK-RV64-NEXT: ret <vscale x 1 x bfloat> [[TMP0]]
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//
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vbfloat16mf4_t test_vloxei32_v_bf16mf4_m(vbool64_t vm, const __bf16 *rs1,
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vuint32mf2_t rs2, size_t vl) {
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return __riscv_vloxei32_v_bf16mf4_m(vm, rs1, rs2, vl);
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}
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// CHECK-RV64-LABEL: define dso_local <vscale x 2 x bfloat> @test_vloxei32_v_bf16mf2_m(
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// CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], ptr noundef [[RS1:%.*]], <vscale x 2 x i32> [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
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// CHECK-RV64-NEXT: entry:
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// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x bfloat> @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat> poison, ptr [[RS1]], <vscale x 2 x i32> [[RS2]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 3)
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// CHECK-RV64-NEXT: ret <vscale x 2 x bfloat> [[TMP0]]
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//
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vbfloat16mf2_t test_vloxei32_v_bf16mf2_m(vbool32_t vm, const __bf16 *rs1,
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vuint32m1_t rs2, size_t vl) {
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return __riscv_vloxei32_v_bf16mf2_m(vm, rs1, rs2, vl);
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}
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// CHECK-RV64-LABEL: define dso_local <vscale x 4 x bfloat> @test_vloxei32_v_bf16m1_m(
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// CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], ptr noundef [[RS1:%.*]], <vscale x 4 x i32> [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
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// CHECK-RV64-NEXT: entry:
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// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x bfloat> @llvm.riscv.vloxei.mask.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat> poison, ptr [[RS1]], <vscale x 4 x i32> [[RS2]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 3)
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// CHECK-RV64-NEXT: ret <vscale x 4 x bfloat> [[TMP0]]
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//
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vbfloat16m1_t test_vloxei32_v_bf16m1_m(vbool16_t vm, const __bf16 *rs1,
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vuint32m2_t rs2, size_t vl) {
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return __riscv_vloxei32_v_bf16m1_m(vm, rs1, rs2, vl);
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}
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// CHECK-RV64-LABEL: define dso_local <vscale x 8 x bfloat> @test_vloxei32_v_bf16m2_m(
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// CHECK-RV64-SAME: <vscale x 8 x i1> [[VM:%.*]], ptr noundef [[RS1:%.*]], <vscale x 8 x i32> [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
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// CHECK-RV64-NEXT: entry:
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// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x bfloat> @llvm.riscv.vloxei.mask.nxv8bf16.p0.nxv8i32.i64(<vscale x 8 x bfloat> poison, ptr [[RS1]], <vscale x 8 x i32> [[RS2]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 3)
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// CHECK-RV64-NEXT: ret <vscale x 8 x bfloat> [[TMP0]]
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//
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vbfloat16m2_t test_vloxei32_v_bf16m2_m(vbool8_t vm, const __bf16 *rs1,
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vuint32m4_t rs2, size_t vl) {
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return __riscv_vloxei32_v_bf16m2_m(vm, rs1, rs2, vl);
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}
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// CHECK-RV64-LABEL: define dso_local <vscale x 16 x bfloat> @test_vloxei32_v_bf16m4_m(
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// CHECK-RV64-SAME: <vscale x 16 x i1> [[VM:%.*]], ptr noundef [[RS1:%.*]], <vscale x 16 x i32> [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
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// CHECK-RV64-NEXT: entry:
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// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x bfloat> @llvm.riscv.vloxei.mask.nxv16bf16.p0.nxv16i32.i64(<vscale x 16 x bfloat> poison, ptr [[RS1]], <vscale x 16 x i32> [[RS2]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 3)
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// CHECK-RV64-NEXT: ret <vscale x 16 x bfloat> [[TMP0]]
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//
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vbfloat16m4_t test_vloxei32_v_bf16m4_m(vbool4_t vm, const __bf16 *rs1,
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vuint32m8_t rs2, size_t vl) {
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return __riscv_vloxei32_v_bf16m4_m(vm, rs1, rs2, vl);
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}

‎clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei64.c

Lines changed: 96 additions & 0 deletions
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// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4
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// REQUIRES: riscv-registered-target
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// RUN: %clang_cc1 -triple riscv64 -target-feature +zve64x \
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// RUN: -target-feature +zvfbfmin -disable-O0-optnone \
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// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
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// RUN: FileCheck --check-prefix=CHECK-RV64 %s
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#include <riscv_vector.h>
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// CHECK-RV64-LABEL: define dso_local <vscale x 1 x bfloat> @test_vloxei64_v_bf16mf4(
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// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], <vscale x 1 x i64> [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
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// CHECK-RV64-NEXT: entry:
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// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x bfloat> @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat> poison, ptr [[RS1]], <vscale x 1 x i64> [[RS2]], i64 [[VL]])
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// CHECK-RV64-NEXT: ret <vscale x 1 x bfloat> [[TMP0]]
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//
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vbfloat16mf4_t test_vloxei64_v_bf16mf4(const __bf16 *rs1, vuint64m1_t rs2,
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size_t vl) {
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return __riscv_vloxei64_v_bf16mf4(rs1, rs2, vl);
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}
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// CHECK-RV64-LABEL: define dso_local <vscale x 2 x bfloat> @test_vloxei64_v_bf16mf2(
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// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], <vscale x 2 x i64> [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
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// CHECK-RV64-NEXT: entry:
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// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x bfloat> @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat> poison, ptr [[RS1]], <vscale x 2 x i64> [[RS2]], i64 [[VL]])
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// CHECK-RV64-NEXT: ret <vscale x 2 x bfloat> [[TMP0]]
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//
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vbfloat16mf2_t test_vloxei64_v_bf16mf2(const __bf16 *rs1, vuint64m2_t rs2,
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size_t vl) {
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return __riscv_vloxei64_v_bf16mf2(rs1, rs2, vl);
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}
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// CHECK-RV64-LABEL: define dso_local <vscale x 4 x bfloat> @test_vloxei64_v_bf16m1(
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// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], <vscale x 4 x i64> [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
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// CHECK-RV64-NEXT: entry:
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// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x bfloat> @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat> poison, ptr [[RS1]], <vscale x 4 x i64> [[RS2]], i64 [[VL]])
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// CHECK-RV64-NEXT: ret <vscale x 4 x bfloat> [[TMP0]]
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//
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vbfloat16m1_t test_vloxei64_v_bf16m1(const __bf16 *rs1, vuint64m4_t rs2,
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size_t vl) {
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return __riscv_vloxei64_v_bf16m1(rs1, rs2, vl);
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}
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// CHECK-RV64-LABEL: define dso_local <vscale x 8 x bfloat> @test_vloxei64_v_bf16m2(
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// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], <vscale x 8 x i64> [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
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// CHECK-RV64-NEXT: entry:
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// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x bfloat> @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i64.i64(<vscale x 8 x bfloat> poison, ptr [[RS1]], <vscale x 8 x i64> [[RS2]], i64 [[VL]])
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// CHECK-RV64-NEXT: ret <vscale x 8 x bfloat> [[TMP0]]
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//
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vbfloat16m2_t test_vloxei64_v_bf16m2(const __bf16 *rs1, vuint64m8_t rs2,
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size_t vl) {
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return __riscv_vloxei64_v_bf16m2(rs1, rs2, vl);
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}
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// CHECK-RV64-LABEL: define dso_local <vscale x 1 x bfloat> @test_vloxei64_v_bf16mf4_m(
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// CHECK-RV64-SAME: <vscale x 1 x i1> [[VM:%.*]], ptr noundef [[RS1:%.*]], <vscale x 1 x i64> [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
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// CHECK-RV64-NEXT: entry:
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// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x bfloat> @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat> poison, ptr [[RS1]], <vscale x 1 x i64> [[RS2]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 3)
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// CHECK-RV64-NEXT: ret <vscale x 1 x bfloat> [[TMP0]]
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//
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vbfloat16mf4_t test_vloxei64_v_bf16mf4_m(vbool64_t vm, const __bf16 *rs1,
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vuint64m1_t rs2, size_t vl) {
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return __riscv_vloxei64_v_bf16mf4_m(vm, rs1, rs2, vl);
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}
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// CHECK-RV64-LABEL: define dso_local <vscale x 2 x bfloat> @test_vloxei64_v_bf16mf2_m(
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// CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], ptr noundef [[RS1:%.*]], <vscale x 2 x i64> [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
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// CHECK-RV64-NEXT: entry:
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// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x bfloat> @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat> poison, ptr [[RS1]], <vscale x 2 x i64> [[RS2]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 3)
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// CHECK-RV64-NEXT: ret <vscale x 2 x bfloat> [[TMP0]]
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//
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vbfloat16mf2_t test_vloxei64_v_bf16mf2_m(vbool32_t vm, const __bf16 *rs1,
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vuint64m2_t rs2, size_t vl) {
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return __riscv_vloxei64_v_bf16mf2_m(vm, rs1, rs2, vl);
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}
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// CHECK-RV64-LABEL: define dso_local <vscale x 4 x bfloat> @test_vloxei64_v_bf16m1_m(
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// CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], ptr noundef [[RS1:%.*]], <vscale x 4 x i64> [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
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// CHECK-RV64-NEXT: entry:
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// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x bfloat> @llvm.riscv.vloxei.mask.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat> poison, ptr [[RS1]], <vscale x 4 x i64> [[RS2]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 3)
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// CHECK-RV64-NEXT: ret <vscale x 4 x bfloat> [[TMP0]]
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//
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vbfloat16m1_t test_vloxei64_v_bf16m1_m(vbool16_t vm, const __bf16 *rs1,
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vuint64m4_t rs2, size_t vl) {
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return __riscv_vloxei64_v_bf16m1_m(vm, rs1, rs2, vl);
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}
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// CHECK-RV64-LABEL: define dso_local <vscale x 8 x bfloat> @test_vloxei64_v_bf16m2_m(
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// CHECK-RV64-SAME: <vscale x 8 x i1> [[VM:%.*]], ptr noundef [[RS1:%.*]], <vscale x 8 x i64> [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
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// CHECK-RV64-NEXT: entry:
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// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x bfloat> @llvm.riscv.vloxei.mask.nxv8bf16.p0.nxv8i64.i64(<vscale x 8 x bfloat> poison, ptr [[RS1]], <vscale x 8 x i64> [[RS2]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 3)
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// CHECK-RV64-NEXT: ret <vscale x 8 x bfloat> [[TMP0]]
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//
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vbfloat16m2_t test_vloxei64_v_bf16m2_m(vbool8_t vm, const __bf16 *rs1,
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vuint64m8_t rs2, size_t vl) {
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return __riscv_vloxei64_v_bf16m2_m(vm, rs1, rs2, vl);
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}

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