VEMCCodeEmitter: Set PCRel at fixup creation

Avoid reliance on the MCAssembler::evaluateFixup workaround that checks
MCFixupKindInfo::FKF_IsPCRel. Additionally, standardize how fixups are
appended. This helper will facilitate future fixup data structure
optimizations.

Author: MaskRay

llvm/lib/Target/VE/MCTargetDesc/VEAsmBackend.cpp

@@ -96,22 +96,14 @@ class VEAsmBackend : public MCAsmBackend {
   MCFixupKindInfo getFixupKindInfo(MCFixupKind Kind) const override {
     const static MCFixupKindInfo Infos[VE::NumTargetFixupKinds] = {
         // name, offset, bits, flags
-        {"fixup_ve_reflong", 0, 32, 0},
-        {"fixup_ve_srel32", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
-        {"fixup_ve_hi32", 0, 32, 0},
-        {"fixup_ve_lo32", 0, 32, 0},
-        {"fixup_ve_pc_hi32", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
-        {"fixup_ve_pc_lo32", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
-        {"fixup_ve_got_hi32", 0, 32, 0},
-        {"fixup_ve_got_lo32", 0, 32, 0},
-        {"fixup_ve_gotoff_hi32", 0, 32, 0},
-        {"fixup_ve_gotoff_lo32", 0, 32, 0},
-        {"fixup_ve_plt_hi32", 0, 32, 0},
-        {"fixup_ve_plt_lo32", 0, 32, 0},
-        {"fixup_ve_tls_gd_hi32", 0, 32, 0},
-        {"fixup_ve_tls_gd_lo32", 0, 32, 0},
-        {"fixup_ve_tpoff_hi32", 0, 32, 0},
-        {"fixup_ve_tpoff_lo32", 0, 32, 0},
+        {"fixup_ve_reflong", 0, 32, 0},     {"fixup_ve_srel32", 0, 32, 0},
+        {"fixup_ve_hi32", 0, 32, 0},        {"fixup_ve_lo32", 0, 32, 0},
+        {"fixup_ve_pc_hi32", 0, 32, 0},     {"fixup_ve_pc_lo32", 0, 32, 0},
+        {"fixup_ve_got_hi32", 0, 32, 0},    {"fixup_ve_got_lo32", 0, 32, 0},
+        {"fixup_ve_gotoff_hi32", 0, 32, 0}, {"fixup_ve_gotoff_lo32", 0, 32, 0},
+        {"fixup_ve_plt_hi32", 0, 32, 0},    {"fixup_ve_plt_lo32", 0, 32, 0},
+        {"fixup_ve_tls_gd_hi32", 0, 32, 0}, {"fixup_ve_tls_gd_lo32", 0, 32, 0},
+        {"fixup_ve_tpoff_hi32", 0, 32, 0},  {"fixup_ve_tpoff_lo32", 0, 32, 0},
     };
 
     if (Kind < FirstTargetFixupKind)

llvm/lib/Target/VE/MCTargetDesc/VEMCCodeEmitter.cpp

@@ -76,6 +76,18 @@ class VEMCCodeEmitter : public MCCodeEmitter {
 
 } // end anonymous namespace
 
+static void addFixup(SmallVectorImpl<MCFixup> &Fixups, uint32_t Offset,
+                     const MCExpr *Value, uint16_t Kind) {
+  bool PCRel = false;
+  switch (Kind) {
+  case VE::fixup_ve_srel32:
+  case VE::fixup_ve_pc_hi32:
+  case VE::fixup_ve_pc_lo32:
+    PCRel = true;
+  }
+  Fixups.push_back(MCFixup::create(Offset, Value, Kind, PCRel));
+}
+
 void VEMCCodeEmitter::encodeInstruction(const MCInst &MI,
                                         SmallVectorImpl<char> &CB,
                                         SmallVectorImpl<MCFixup> &Fixups,
@@ -100,7 +112,7 @@ unsigned VEMCCodeEmitter::getMachineOpValue(const MCInst &MI,
   const MCExpr *Expr = MO.getExpr();
   if (const auto *SExpr = dyn_cast<MCSpecifierExpr>(Expr)) {
     auto Kind = VE::getFixupKind(SExpr->getSpecifier());
-    Fixups.push_back(MCFixup::create(0, Expr, Kind));
+    addFixup(Fixups, 0, Expr, Kind);
     return 0;
   }
 
@@ -120,8 +132,7 @@ VEMCCodeEmitter::getBranchTargetOpValue(const MCInst &MI, unsigned OpNo,
   if (MO.isReg() || MO.isImm())
     return getMachineOpValue(MI, MO, Fixups, STI);
 
-  Fixups.push_back(
-      MCFixup::create(0, MO.getExpr(), (MCFixupKind)VE::fixup_ve_srel32));
+  addFixup(Fixups, 0, MO.getExpr(), VE::fixup_ve_srel32);
   return 0;
 }