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[RISCV] Add LLVM IR intrinsicis vrgatherei16/vslideup/vslidedown support for Zvfbfmin (#146312)
This patch add LLVM IR intrinsicis vrgatherei16/vslideup/vslidedown support for Zvfbfmin.
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4 files changed

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‎llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -7419,6 +7419,9 @@ defm : VPatTernaryV_VX_VI<"int_riscv_vslidedown", "PseudoVSLIDEDOWN", AllFloatVe
74197419
defm : VPatBinaryV_VX<"int_riscv_vfslide1up", "PseudoVFSLIDE1UP", AllFloatVectors>;
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defm : VPatBinaryV_VX<"int_riscv_vfslide1down", "PseudoVFSLIDE1DOWN", AllFloatVectors>;
74217421

7422+
defm : VPatTernaryV_VX_VI<"int_riscv_vslideup", "PseudoVSLIDEUP", AllBFloatVectors, uimm5>;
7423+
defm : VPatTernaryV_VX_VI<"int_riscv_vslidedown", "PseudoVSLIDEDOWN", AllBFloatVectors, uimm5>;
7424+
74227425
//===----------------------------------------------------------------------===//
74237426
// 16.4. Vector Register Gather Instructions
74247427
//===----------------------------------------------------------------------===//
@@ -7433,6 +7436,8 @@ defm : VPatBinaryV_VV_VX_VI_INT<"int_riscv_vrgather", "PseudoVRGATHER",
74337436
AllBFloatVectors, uimm5>;
74347437
defm : VPatBinaryV_VV_INT_EEW<"int_riscv_vrgatherei16_vv", "PseudoVRGATHEREI16",
74357438
eew=16, vtilist=AllFloatVectors>;
7439+
defm : VPatBinaryV_VV_INT_EEW<"int_riscv_vrgatherei16_vv", "PseudoVRGATHEREI16",
7440+
eew=16, vtilist=AllBFloatVectors>;
74367441
//===----------------------------------------------------------------------===//
74377442
// 16.5. Vector Compress Instruction
74387443
//===----------------------------------------------------------------------===//

‎llvm/test/CodeGen/RISCV/rvv/vrgatherei16.ll

Lines changed: 207 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,7 @@
11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2-
; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+d,+zvfhmin \
2+
; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+d,+zvfhmin,+zvfbfmin \
33
; RUN: -verify-machineinstrs | FileCheck %s
4-
; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+d,+zvfhmin \
4+
; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+d,+zvfhmin,+zvfbfmin \
55
; RUN: -verify-machineinstrs | FileCheck %s
66

77
declare <vscale x 1 x i8> @llvm.riscv.vrgatherei16.vv.nxv1i8(
@@ -1449,3 +1449,208 @@ entry:
14491449

14501450
ret <vscale x 8 x double> %a
14511451
}
1452+
1453+
define <vscale x 1 x bfloat> @intrinsic_vrgatherei16_vv_nxv1bf16_nxv1bf16(<vscale x 1 x bfloat> %0, <vscale x 1 x i16> %1, iXLen %2) nounwind {
1454+
; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv1bf16_nxv1bf16:
1455+
; CHECK: # %bb.0: # %entry
1456+
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
1457+
; CHECK-NEXT: vrgatherei16.vv v10, v8, v9
1458+
; CHECK-NEXT: vmv1r.v v8, v10
1459+
; CHECK-NEXT: ret
1460+
entry:
1461+
%a = call <vscale x 1 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv1bf16(
1462+
<vscale x 1 x bfloat> undef,
1463+
<vscale x 1 x bfloat> %0,
1464+
<vscale x 1 x i16> %1,
1465+
iXLen %2)
1466+
1467+
ret <vscale x 1 x bfloat> %a
1468+
}
1469+
1470+
define <vscale x 1 x bfloat> @intrinsic_vrgatherei16_mask_vv_nxv1bf16_nxv1bf16(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
1471+
; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv1bf16_nxv1bf16:
1472+
; CHECK: # %bb.0: # %entry
1473+
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
1474+
; CHECK-NEXT: vrgatherei16.vv v8, v9, v10, v0.t
1475+
; CHECK-NEXT: ret
1476+
entry:
1477+
%a = call <vscale x 1 x bfloat> @llvm.riscv.vrgatherei16.vv.mask.nxv1bf16(
1478+
<vscale x 1 x bfloat> %0,
1479+
<vscale x 1 x bfloat> %1,
1480+
<vscale x 1 x i16> %2,
1481+
<vscale x 1 x i1> %3,
1482+
iXLen %4, iXLen 1)
1483+
1484+
ret <vscale x 1 x bfloat> %a
1485+
}
1486+
1487+
define <vscale x 2 x bfloat> @intrinsic_vrgatherei16_vv_nxv2bf16_nxv2bf16(<vscale x 2 x bfloat> %0, <vscale x 2 x i16> %1, iXLen %2) nounwind {
1488+
; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv2bf16_nxv2bf16:
1489+
; CHECK: # %bb.0: # %entry
1490+
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
1491+
; CHECK-NEXT: vrgatherei16.vv v10, v8, v9
1492+
; CHECK-NEXT: vmv1r.v v8, v10
1493+
; CHECK-NEXT: ret
1494+
entry:
1495+
%a = call <vscale x 2 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv2bf16(
1496+
<vscale x 2 x bfloat> undef,
1497+
<vscale x 2 x bfloat> %0,
1498+
<vscale x 2 x i16> %1,
1499+
iXLen %2)
1500+
1501+
ret <vscale x 2 x bfloat> %a
1502+
}
1503+
1504+
define <vscale x 2 x bfloat> @intrinsic_vrgatherei16_mask_vv_nxv2bf16_nxv2bf16(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
1505+
; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv2bf16_nxv2bf16:
1506+
; CHECK: # %bb.0: # %entry
1507+
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
1508+
; CHECK-NEXT: vrgatherei16.vv v8, v9, v10, v0.t
1509+
; CHECK-NEXT: ret
1510+
entry:
1511+
%a = call <vscale x 2 x bfloat> @llvm.riscv.vrgatherei16.vv.mask.nxv2bf16(
1512+
<vscale x 2 x bfloat> %0,
1513+
<vscale x 2 x bfloat> %1,
1514+
<vscale x 2 x i16> %2,
1515+
<vscale x 2 x i1> %3,
1516+
iXLen %4, iXLen 1)
1517+
1518+
ret <vscale x 2 x bfloat> %a
1519+
}
1520+
1521+
define <vscale x 4 x bfloat> @intrinsic_vrgatherei16_vv_nxv4bf16_nxv4bf16(<vscale x 4 x bfloat> %0, <vscale x 4 x i16> %1, iXLen %2) nounwind {
1522+
; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv4bf16_nxv4bf16:
1523+
; CHECK: # %bb.0: # %entry
1524+
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
1525+
; CHECK-NEXT: vrgatherei16.vv v10, v8, v9
1526+
; CHECK-NEXT: vmv.v.v v8, v10
1527+
; CHECK-NEXT: ret
1528+
entry:
1529+
%a = call <vscale x 4 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv4bf16(
1530+
<vscale x 4 x bfloat> undef,
1531+
<vscale x 4 x bfloat> %0,
1532+
<vscale x 4 x i16> %1,
1533+
iXLen %2)
1534+
1535+
ret <vscale x 4 x bfloat> %a
1536+
}
1537+
1538+
define <vscale x 4 x bfloat> @intrinsic_vrgatherei16_mask_vv_nxv4bf16_nxv4bf16(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
1539+
; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv4bf16_nxv4bf16:
1540+
; CHECK: # %bb.0: # %entry
1541+
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
1542+
; CHECK-NEXT: vrgatherei16.vv v8, v9, v10, v0.t
1543+
; CHECK-NEXT: ret
1544+
entry:
1545+
%a = call <vscale x 4 x bfloat> @llvm.riscv.vrgatherei16.vv.mask.nxv4bf16(
1546+
<vscale x 4 x bfloat> %0,
1547+
<vscale x 4 x bfloat> %1,
1548+
<vscale x 4 x i16> %2,
1549+
<vscale x 4 x i1> %3,
1550+
iXLen %4, iXLen 1)
1551+
1552+
ret <vscale x 4 x bfloat> %a
1553+
}
1554+
1555+
define <vscale x 8 x bfloat> @intrinsic_vrgatherei16_vv_nxv8bf16_nxv8bf16(<vscale x 8 x bfloat> %0, <vscale x 8 x i16> %1, iXLen %2) nounwind {
1556+
; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv8bf16_nxv8bf16:
1557+
; CHECK: # %bb.0: # %entry
1558+
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
1559+
; CHECK-NEXT: vrgatherei16.vv v12, v8, v10
1560+
; CHECK-NEXT: vmv.v.v v8, v12
1561+
; CHECK-NEXT: ret
1562+
entry:
1563+
%a = call <vscale x 8 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv8bf16(
1564+
<vscale x 8 x bfloat> undef,
1565+
<vscale x 8 x bfloat> %0,
1566+
<vscale x 8 x i16> %1,
1567+
iXLen %2)
1568+
1569+
ret <vscale x 8 x bfloat> %a
1570+
}
1571+
1572+
define <vscale x 8 x bfloat> @intrinsic_vrgatherei16_mask_vv_nxv8bf16_nxv8bf16(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
1573+
; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv8bf16_nxv8bf16:
1574+
; CHECK: # %bb.0: # %entry
1575+
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
1576+
; CHECK-NEXT: vrgatherei16.vv v8, v10, v12, v0.t
1577+
; CHECK-NEXT: ret
1578+
entry:
1579+
%a = call <vscale x 8 x bfloat> @llvm.riscv.vrgatherei16.vv.mask.nxv8bf16(
1580+
<vscale x 8 x bfloat> %0,
1581+
<vscale x 8 x bfloat> %1,
1582+
<vscale x 8 x i16> %2,
1583+
<vscale x 8 x i1> %3,
1584+
iXLen %4, iXLen 1)
1585+
1586+
ret <vscale x 8 x bfloat> %a
1587+
}
1588+
1589+
define <vscale x 16 x bfloat> @intrinsic_vrgatherei16_vv_nxv16bf16_nxv16bf16(<vscale x 16 x bfloat> %0, <vscale x 16 x i16> %1, iXLen %2) nounwind {
1590+
; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv16bf16_nxv16bf16:
1591+
; CHECK: # %bb.0: # %entry
1592+
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
1593+
; CHECK-NEXT: vrgatherei16.vv v16, v8, v12
1594+
; CHECK-NEXT: vmv.v.v v8, v16
1595+
; CHECK-NEXT: ret
1596+
entry:
1597+
%a = call <vscale x 16 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv16bf16(
1598+
<vscale x 16 x bfloat> undef,
1599+
<vscale x 16 x bfloat> %0,
1600+
<vscale x 16 x i16> %1,
1601+
iXLen %2)
1602+
1603+
ret <vscale x 16 x bfloat> %a
1604+
}
1605+
1606+
define <vscale x 16 x bfloat> @intrinsic_vrgatherei16_mask_vv_nxv16bf16_nxv16bf16(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {
1607+
; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv16bf16_nxv16bf16:
1608+
; CHECK: # %bb.0: # %entry
1609+
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
1610+
; CHECK-NEXT: vrgatherei16.vv v8, v12, v16, v0.t
1611+
; CHECK-NEXT: ret
1612+
entry:
1613+
%a = call <vscale x 16 x bfloat> @llvm.riscv.vrgatherei16.vv.mask.nxv16bf16(
1614+
<vscale x 16 x bfloat> %0,
1615+
<vscale x 16 x bfloat> %1,
1616+
<vscale x 16 x i16> %2,
1617+
<vscale x 16 x i1> %3,
1618+
iXLen %4, iXLen 1)
1619+
1620+
ret <vscale x 16 x bfloat> %a
1621+
}
1622+
1623+
define <vscale x 32 x bfloat> @intrinsic_vrgatherei16_vv_nxv32bf16_nxv32bf16(<vscale x 32 x bfloat> %0, <vscale x 32 x i16> %1, iXLen %2) nounwind {
1624+
; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv32bf16_nxv32bf16:
1625+
; CHECK: # %bb.0: # %entry
1626+
; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma
1627+
; CHECK-NEXT: vrgatherei16.vv v24, v8, v16
1628+
; CHECK-NEXT: vmv.v.v v8, v24
1629+
; CHECK-NEXT: ret
1630+
entry:
1631+
%a = call <vscale x 32 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv32bf16(
1632+
<vscale x 32 x bfloat> undef,
1633+
<vscale x 32 x bfloat> %0,
1634+
<vscale x 32 x i16> %1,
1635+
iXLen %2)
1636+
1637+
ret <vscale x 32 x bfloat> %a
1638+
}
1639+
1640+
define <vscale x 32 x bfloat> @intrinsic_vrgatherei16_mask_vv_nxv32bf16_nxv32bf16(<vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, iXLen %4) nounwind {
1641+
; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv32bf16_nxv32bf16:
1642+
; CHECK: # %bb.0: # %entry
1643+
; CHECK-NEXT: vl8re16.v v24, (a0)
1644+
; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu
1645+
; CHECK-NEXT: vrgatherei16.vv v8, v16, v24, v0.t
1646+
; CHECK-NEXT: ret
1647+
entry:
1648+
%a = call <vscale x 32 x bfloat> @llvm.riscv.vrgatherei16.vv.mask.nxv32bf16(
1649+
<vscale x 32 x bfloat> %0,
1650+
<vscale x 32 x bfloat> %1,
1651+
<vscale x 32 x i16> %2,
1652+
<vscale x 32 x i1> %3,
1653+
iXLen %4, iXLen 1)
1654+
1655+
ret <vscale x 32 x bfloat> %a
1656+
}

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