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[NFC][LLVM][SVE] Add bfloat predicated binop and FMA tests.
This is a bfloat clone of sve-fp-combine.ll that only tests sve-b16b16 because without this feature all binops are expanded to float.
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‎llvm/test/CodeGen/AArch64/sve-bf16-combines.ll

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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mattr=+sve,+bf16,+sve-b16b16 < %s | FileCheck %s
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target triple = "aarch64-unknown-linux-gnu"
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define <vscale x 8 x bfloat> @fmla_nxv8bf16(<vscale x 8 x bfloat> %acc, <vscale x 8 x bfloat> %m1, <vscale x 8 x bfloat> %m2) {
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; CHECK-LABEL: fmla_nxv8bf16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: bfmul z1.h, z1.h, z2.h
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; CHECK-NEXT: bfadd z0.h, z0.h, z1.h
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; CHECK-NEXT: ret
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%mul = fmul contract <vscale x 8 x bfloat> %m1, %m2
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%res = fadd contract <vscale x 8 x bfloat> %acc, %mul
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ret <vscale x 8 x bfloat> %res
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}
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define <vscale x 4 x bfloat> @fmla_nxv4bf16(<vscale x 4 x bfloat> %acc, <vscale x 4 x bfloat> %m1, <vscale x 4 x bfloat> %m2) {
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; CHECK-LABEL: fmla_nxv4bf16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: bfmul z1.h, z1.h, z2.h
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; CHECK-NEXT: bfadd z0.h, z0.h, z1.h
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; CHECK-NEXT: ret
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%mul = fmul contract <vscale x 4 x bfloat> %m1, %m2
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%res = fadd contract <vscale x 4 x bfloat> %acc, %mul
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ret <vscale x 4 x bfloat> %res
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}
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define <vscale x 2 x bfloat> @fmla_nxv2bf16(<vscale x 2 x bfloat> %acc, <vscale x 2 x bfloat> %m1, <vscale x 2 x bfloat> %m2) {
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; CHECK-LABEL: fmla_nxv2bf16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: bfmul z1.h, z1.h, z2.h
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; CHECK-NEXT: bfadd z0.h, z0.h, z1.h
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; CHECK-NEXT: ret
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%mul = fmul contract <vscale x 2 x bfloat> %m1, %m2
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%res = fadd contract <vscale x 2 x bfloat> %acc, %mul
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ret <vscale x 2 x bfloat> %res
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}
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define <vscale x 8 x bfloat> @fmls_nxv8bf16(<vscale x 8 x bfloat> %acc, <vscale x 8 x bfloat> %m1, <vscale x 8 x bfloat> %m2) {
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; CHECK-LABEL: fmls_nxv8bf16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: bfmul z1.h, z1.h, z2.h
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; CHECK-NEXT: bfsub z0.h, z0.h, z1.h
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; CHECK-NEXT: ret
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%mul = fmul contract <vscale x 8 x bfloat> %m1, %m2
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%res = fsub contract <vscale x 8 x bfloat> %acc, %mul
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ret <vscale x 8 x bfloat> %res
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}
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define <vscale x 4 x bfloat> @fmls_nxv4bf16(<vscale x 4 x bfloat> %acc, <vscale x 4 x bfloat> %m1, <vscale x 4 x bfloat> %m2) {
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; CHECK-LABEL: fmls_nxv4bf16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: bfmul z1.h, z1.h, z2.h
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; CHECK-NEXT: bfsub z0.h, z0.h, z1.h
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; CHECK-NEXT: ret
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%mul = fmul contract <vscale x 4 x bfloat> %m1, %m2
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%res = fsub contract <vscale x 4 x bfloat> %acc, %mul
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ret <vscale x 4 x bfloat> %res
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}
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define <vscale x 2 x bfloat> @fmls_nxv2bf16(<vscale x 2 x bfloat> %acc, <vscale x 2 x bfloat> %m1, <vscale x 2 x bfloat> %m2) {
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; CHECK-LABEL: fmls_nxv2bf16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: bfmul z1.h, z1.h, z2.h
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; CHECK-NEXT: bfsub z0.h, z0.h, z1.h
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; CHECK-NEXT: ret
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%mul = fmul contract <vscale x 2 x bfloat> %m1, %m2
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%res = fsub contract <vscale x 2 x bfloat> %acc, %mul
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ret <vscale x 2 x bfloat> %res
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}
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define <vscale x 8 x bfloat> @fmla_sel_nxv8bf16(<vscale x 8 x i1> %pred, <vscale x 8 x bfloat> %acc, <vscale x 8 x bfloat> %m1, <vscale x 8 x bfloat> %m2) {
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; CHECK-LABEL: fmla_sel_nxv8bf16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: bfmul z1.h, z1.h, z2.h
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; CHECK-NEXT: bfadd z1.h, z0.h, z1.h
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; CHECK-NEXT: mov z0.h, p0/m, z1.h
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; CHECK-NEXT: ret
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%mul = fmul contract <vscale x 8 x bfloat> %m1, %m2
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%add = fadd contract <vscale x 8 x bfloat> %acc, %mul
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%res = select <vscale x 8 x i1> %pred, <vscale x 8 x bfloat> %add, <vscale x 8 x bfloat> %acc
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ret <vscale x 8 x bfloat> %res
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}
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define <vscale x 4 x bfloat> @fmla_sel_nxv4bf16(<vscale x 4 x i1> %pred, <vscale x 4 x bfloat> %acc, <vscale x 4 x bfloat> %m1, <vscale x 4 x bfloat> %m2) {
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; CHECK-LABEL: fmla_sel_nxv4bf16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: bfmul z1.h, z1.h, z2.h
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; CHECK-NEXT: bfadd z1.h, z0.h, z1.h
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; CHECK-NEXT: mov z0.s, p0/m, z1.s
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; CHECK-NEXT: ret
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%mul = fmul contract <vscale x 4 x bfloat> %m1, %m2
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%add = fadd contract <vscale x 4 x bfloat> %acc, %mul
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%res = select <vscale x 4 x i1> %pred, <vscale x 4 x bfloat> %add, <vscale x 4 x bfloat> %acc
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ret <vscale x 4 x bfloat> %res
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}
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define <vscale x 2 x bfloat> @fmla_sel_nxv2bf16(<vscale x 2 x i1> %pred, <vscale x 2 x bfloat> %acc, <vscale x 2 x bfloat> %m1, <vscale x 2 x bfloat> %m2) {
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; CHECK-LABEL: fmla_sel_nxv2bf16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: bfmul z1.h, z1.h, z2.h
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; CHECK-NEXT: bfadd z1.h, z0.h, z1.h
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; CHECK-NEXT: mov z0.d, p0/m, z1.d
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; CHECK-NEXT: ret
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%mul = fmul contract <vscale x 2 x bfloat> %m1, %m2
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%add = fadd contract <vscale x 2 x bfloat> %acc, %mul
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%res = select <vscale x 2 x i1> %pred, <vscale x 2 x bfloat> %add, <vscale x 2 x bfloat> %acc
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ret <vscale x 2 x bfloat> %res
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}
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define <vscale x 8 x bfloat> @fmls_sel_nxv8bf16(<vscale x 8 x i1> %pred, <vscale x 8 x bfloat> %acc, <vscale x 8 x bfloat> %m1, <vscale x 8 x bfloat> %m2) {
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; CHECK-LABEL: fmls_sel_nxv8bf16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: bfmul z1.h, z1.h, z2.h
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; CHECK-NEXT: bfsub z1.h, z0.h, z1.h
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; CHECK-NEXT: mov z0.h, p0/m, z1.h
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; CHECK-NEXT: ret
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%mul = fmul contract <vscale x 8 x bfloat> %m1, %m2
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%sub = fsub contract <vscale x 8 x bfloat> %acc, %mul
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%res = select <vscale x 8 x i1> %pred, <vscale x 8 x bfloat> %sub, <vscale x 8 x bfloat> %acc
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ret <vscale x 8 x bfloat> %res
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}
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define <vscale x 4 x bfloat> @fmls_sel_nxv4bf16(<vscale x 4 x i1> %pred, <vscale x 4 x bfloat> %acc, <vscale x 4 x bfloat> %m1, <vscale x 4 x bfloat> %m2) {
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; CHECK-LABEL: fmls_sel_nxv4bf16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: bfmul z1.h, z1.h, z2.h
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; CHECK-NEXT: bfsub z1.h, z0.h, z1.h
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; CHECK-NEXT: mov z0.s, p0/m, z1.s
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; CHECK-NEXT: ret
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%mul = fmul contract <vscale x 4 x bfloat> %m1, %m2
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%sub = fsub contract <vscale x 4 x bfloat> %acc, %mul
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%res = select <vscale x 4 x i1> %pred, <vscale x 4 x bfloat> %sub, <vscale x 4 x bfloat> %acc
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ret <vscale x 4 x bfloat> %res
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}
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define <vscale x 2 x bfloat> @fmls_sel_nxv2bf16(<vscale x 2 x i1> %pred, <vscale x 2 x bfloat> %acc, <vscale x 2 x bfloat> %m1, <vscale x 2 x bfloat> %m2) {
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; CHECK-LABEL: fmls_sel_nxv2bf16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: bfmul z1.h, z1.h, z2.h
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; CHECK-NEXT: bfsub z1.h, z0.h, z1.h
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; CHECK-NEXT: mov z0.d, p0/m, z1.d
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; CHECK-NEXT: ret
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%mul = fmul contract <vscale x 2 x bfloat> %m1, %m2
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%sub = fsub contract <vscale x 2 x bfloat> %acc, %mul
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%res = select <vscale x 2 x i1> %pred, <vscale x 2 x bfloat> %sub, <vscale x 2 x bfloat> %acc
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ret <vscale x 2 x bfloat> %res
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}
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define <vscale x 8 x bfloat> @fadd_sel_nxv8bf16(<vscale x 8 x bfloat> %a, <vscale x 8 x bfloat> %b, <vscale x 8 x i1> %mask) {
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; CHECK-LABEL: fadd_sel_nxv8bf16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: bfadd z1.h, z0.h, z1.h
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; CHECK-NEXT: mov z0.h, p0/m, z1.h
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; CHECK-NEXT: ret
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%sel = select <vscale x 8 x i1> %mask, <vscale x 8 x bfloat> %b, <vscale x 8 x bfloat> zeroinitializer
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%fadd = fadd nsz <vscale x 8 x bfloat> %a, %sel
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ret <vscale x 8 x bfloat> %fadd
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}
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define <vscale x 8 x bfloat> @fsub_sel_nxv8bf16(<vscale x 8 x bfloat> %a, <vscale x 8 x bfloat> %b, <vscale x 8 x i1> %mask) {
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; CHECK-LABEL: fsub_sel_nxv8bf16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: bfsub z1.h, z0.h, z1.h
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; CHECK-NEXT: mov z0.h, p0/m, z1.h
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; CHECK-NEXT: ret
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%sel = select <vscale x 8 x i1> %mask, <vscale x 8 x bfloat> %b, <vscale x 8 x bfloat> zeroinitializer
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%fsub = fsub <vscale x 8 x bfloat> %a, %sel
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ret <vscale x 8 x bfloat> %fsub
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}
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define <vscale x 8 x bfloat> @fadd_sel_negzero_nxv8bf16(<vscale x 8 x bfloat> %a, <vscale x 8 x bfloat> %b, <vscale x 8 x i1> %mask) {
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; CHECK-LABEL: fadd_sel_negzero_nxv8bf16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: bfadd z1.h, z0.h, z1.h
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; CHECK-NEXT: mov z0.h, p0/m, z1.h
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; CHECK-NEXT: ret
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%nz = fneg <vscale x 8 x bfloat> zeroinitializer
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%sel = select <vscale x 8 x i1> %mask, <vscale x 8 x bfloat> %b, <vscale x 8 x bfloat> %nz
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%fadd = fadd <vscale x 8 x bfloat> %a, %sel
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ret <vscale x 8 x bfloat> %fadd
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}
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define <vscale x 8 x bfloat> @fsub_sel_negzero_nxv8bf16(<vscale x 8 x bfloat> %a, <vscale x 8 x bfloat> %b, <vscale x 8 x i1> %mask) {
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; CHECK-LABEL: fsub_sel_negzero_nxv8bf16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: bfsub z1.h, z0.h, z1.h
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; CHECK-NEXT: mov z0.h, p0/m, z1.h
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; CHECK-NEXT: ret
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%nz = fneg <vscale x 8 x bfloat> zeroinitializer
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%sel = select <vscale x 8 x i1> %mask, <vscale x 8 x bfloat> %b, <vscale x 8 x bfloat> %nz
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%fsub = fsub nsz <vscale x 8 x bfloat> %a, %sel
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ret <vscale x 8 x bfloat> %fsub
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}
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define <vscale x 8 x bfloat> @fadd_sel_fmul_nxv8bf16(<vscale x 8 x bfloat> %a, <vscale x 8 x bfloat> %b, <vscale x 8 x bfloat> %c, <vscale x 8 x i1> %mask) {
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; CHECK-LABEL: fadd_sel_fmul_nxv8bf16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: movi v3.2d, #0000000000000000
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; CHECK-NEXT: bfmul z1.h, z1.h, z2.h
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; CHECK-NEXT: sel z1.h, p0, z1.h, z3.h
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; CHECK-NEXT: bfadd z0.h, z0.h, z1.h
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; CHECK-NEXT: ret
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%fmul = fmul <vscale x 8 x bfloat> %b, %c
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%sel = select <vscale x 8 x i1> %mask, <vscale x 8 x bfloat> %fmul, <vscale x 8 x bfloat> zeroinitializer
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%fadd = fadd contract <vscale x 8 x bfloat> %a, %sel
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ret <vscale x 8 x bfloat> %fadd
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}
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define <vscale x 8 x bfloat> @fsub_sel_fmul_nxv8bf16(<vscale x 8 x bfloat> %a, <vscale x 8 x bfloat> %b, <vscale x 8 x bfloat> %c, <vscale x 8 x i1> %mask) {
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; CHECK-LABEL: fsub_sel_fmul_nxv8bf16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: bfmul z1.h, z1.h, z2.h
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; CHECK-NEXT: bfsub z1.h, z0.h, z1.h
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; CHECK-NEXT: mov z0.h, p0/m, z1.h
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; CHECK-NEXT: ret
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%fmul = fmul <vscale x 8 x bfloat> %b, %c
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%sel = select <vscale x 8 x i1> %mask, <vscale x 8 x bfloat> %fmul, <vscale x 8 x bfloat> zeroinitializer
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%fsub = fsub contract <vscale x 8 x bfloat> %a, %sel
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ret <vscale x 8 x bfloat> %fsub
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}
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define <vscale x 8 x bfloat> @fadd_sel_fmul_nsz_nxv8bf16(<vscale x 8 x bfloat> %a, <vscale x 8 x bfloat> %b, <vscale x 8 x bfloat> %c, <vscale x 8 x i1> %mask) {
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; CHECK-LABEL: fadd_sel_fmul_nsz_nxv8bf16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: bfmul z1.h, z1.h, z2.h
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; CHECK-NEXT: bfadd z1.h, z0.h, z1.h
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; CHECK-NEXT: mov z0.h, p0/m, z1.h
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; CHECK-NEXT: ret
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%fmul = fmul <vscale x 8 x bfloat> %b, %c
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%sel = select <vscale x 8 x i1> %mask, <vscale x 8 x bfloat> %fmul, <vscale x 8 x bfloat> zeroinitializer
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%fadd = fadd nsz contract <vscale x 8 x bfloat> %a, %sel
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ret <vscale x 8 x bfloat> %fadd
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}
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define <vscale x 8 x bfloat> @fsub_sel_fmul_nsz_nxv8bf16(<vscale x 8 x bfloat> %a, <vscale x 8 x bfloat> %b, <vscale x 8 x bfloat> %c, <vscale x 8 x i1> %mask) {
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; CHECK-LABEL: fsub_sel_fmul_nsz_nxv8bf16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: bfmul z1.h, z1.h, z2.h
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; CHECK-NEXT: bfsub z1.h, z0.h, z1.h
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; CHECK-NEXT: mov z0.h, p0/m, z1.h
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; CHECK-NEXT: ret
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%fmul = fmul <vscale x 8 x bfloat> %b, %c
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%sel = select <vscale x 8 x i1> %mask, <vscale x 8 x bfloat> %fmul, <vscale x 8 x bfloat> zeroinitializer
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%fsub = fsub nsz contract <vscale x 8 x bfloat> %a, %sel
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ret <vscale x 8 x bfloat> %fsub
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}
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define <vscale x 8 x bfloat> @fadd_sel_fmul_negzero_nxv8bf16(<vscale x 8 x bfloat> %a, <vscale x 8 x bfloat> %b, <vscale x 8 x bfloat> %c, <vscale x 8 x i1> %mask) {
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; CHECK-LABEL: fadd_sel_fmul_negzero_nxv8bf16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: bfmul z1.h, z1.h, z2.h
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; CHECK-NEXT: bfadd z1.h, z0.h, z1.h
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; CHECK-NEXT: mov z0.h, p0/m, z1.h
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; CHECK-NEXT: ret
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%fmul = fmul <vscale x 8 x bfloat> %b, %c
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%nz = fneg <vscale x 8 x bfloat> zeroinitializer
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%sel = select <vscale x 8 x i1> %mask, <vscale x 8 x bfloat> %fmul, <vscale x 8 x bfloat> %nz
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%fadd = fadd contract <vscale x 8 x bfloat> %a, %sel
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ret <vscale x 8 x bfloat> %fadd
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}
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define <vscale x 8 x bfloat> @fsub_sel_fmul_negzero_nxv8bf16(<vscale x 8 x bfloat> %a, <vscale x 8 x bfloat> %b, <vscale x 8 x bfloat> %c, <vscale x 8 x i1> %mask) {
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; CHECK-LABEL: fsub_sel_fmul_negzero_nxv8bf16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov w8, #32768 // =0x8000
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; CHECK-NEXT: bfmul z1.h, z1.h, z2.h
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; CHECK-NEXT: fmov h3, w8
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; CHECK-NEXT: mov z3.h, h3
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; CHECK-NEXT: sel z1.h, p0, z1.h, z3.h
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; CHECK-NEXT: bfsub z0.h, z0.h, z1.h
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; CHECK-NEXT: ret
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%fmul = fmul <vscale x 8 x bfloat> %b, %c
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%nz = fneg <vscale x 8 x bfloat> zeroinitializer
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%sel = select <vscale x 8 x i1> %mask, <vscale x 8 x bfloat> %fmul, <vscale x 8 x bfloat> %nz
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%fsub = fsub contract <vscale x 8 x bfloat> %a, %sel
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ret <vscale x 8 x bfloat> %fsub
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}
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define <vscale x 8 x bfloat> @fadd_sel_fmul_negzero_nsz_nxv8bf16(<vscale x 8 x bfloat> %a, <vscale x 8 x bfloat> %b, <vscale x 8 x bfloat> %c, <vscale x 8 x i1> %mask) {
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; CHECK-LABEL: fadd_sel_fmul_negzero_nsz_nxv8bf16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: bfmul z1.h, z1.h, z2.h
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; CHECK-NEXT: bfadd z1.h, z0.h, z1.h
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; CHECK-NEXT: mov z0.h, p0/m, z1.h
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; CHECK-NEXT: ret
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%fmul = fmul <vscale x 8 x bfloat> %b, %c
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%nz = fneg <vscale x 8 x bfloat> zeroinitializer
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%sel = select <vscale x 8 x i1> %mask, <vscale x 8 x bfloat> %fmul, <vscale x 8 x bfloat> %nz
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%fadd = fadd nsz contract <vscale x 8 x bfloat> %a, %sel
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ret <vscale x 8 x bfloat> %fadd
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}
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define <vscale x 8 x bfloat> @fsub_sel_fmul_negzero_nsz_nxv8bf16(<vscale x 8 x bfloat> %a, <vscale x 8 x bfloat> %b, <vscale x 8 x bfloat> %c, <vscale x 8 x i1> %mask) {
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; CHECK-LABEL: fsub_sel_fmul_negzero_nsz_nxv8bf16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: bfmul z1.h, z1.h, z2.h
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; CHECK-NEXT: bfsub z1.h, z0.h, z1.h
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; CHECK-NEXT: mov z0.h, p0/m, z1.h
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; CHECK-NEXT: ret
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%fmul = fmul <vscale x 8 x bfloat> %b, %c
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%nz = fneg <vscale x 8 x bfloat> zeroinitializer
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%sel = select <vscale x 8 x i1> %mask, <vscale x 8 x bfloat> %fmul, <vscale x 8 x bfloat> %nz
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%fsub = fsub nsz contract <vscale x 8 x bfloat> %a, %sel
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ret <vscale x 8 x bfloat> %fsub
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}
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declare <vscale x 8 x bfloat> @llvm.fma.nxv8bf16(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>)

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