[RISCV][Xqcili] Implement Load Immediate Support (#132496)

This is required to support `li`, but the code is also shared with
CodeGen so the compiler will now emit instructions from Xqcili when that
extension is enabled during compilation.

Also implemented some missed verifiers in
`RISCVInstrInfo::verifyInstruction`, some of which are required for this
change.

Author: lenary

llvm/docs/ReleaseNotes.md

@@ -150,6 +150,8 @@ Changes to the RISC-V Backend
 * Adds Support for Qualcomm's `qci-nest` and `qci-nonest` interrupt types, which
   use instructions from `Xqciint` to save and restore some GPRs during interrupt
   handlers.
+* When the experimental extension `Xqcili` is enabled, `qc.e.li` and `qc.li` may
+  now be used to materialize immediates.
 
 Changes to the WebAssembly Backend
 ----------------------------------

llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp

@@ -22,6 +22,10 @@ static int getInstSeqCost(RISCVMatInt::InstSeq &Res, bool HasRVC) {
     // Assume instructions that aren't listed aren't compressible.
     bool Compressed = false;
     switch (Instr.getOpcode()) {
+    case RISCV::QC_E_LI:
+      // One 48-bit instruction takes the space of 1.5 regular instructions.
+      Cost += 150;
+      continue;
     case RISCV::SLLI:
     case RISCV::SRLI:
       Compressed = true;
@@ -57,6 +61,24 @@ static void generateInstSeqImpl(int64_t Val, const MCSubtargetInfo &STI,
     return;
   }
 
+  if (!IsRV64 && STI.hasFeature(RISCV::FeatureVendorXqcili)) {
+    bool FitsOneStandardInst = ((Val & 0xFFF) == 0) || isInt<12>(Val);
+
+    // 20-bit signed immediates that don't fit into `ADDI` or `LUI` should use
+    // `QC.LI` (a single 32-bit instruction).
+    if (!FitsOneStandardInst && isInt<20>(Val)) {
+      Res.emplace_back(RISCV::QC_LI, Val);
+      return;
+    }
+
+    // 32-bit signed immediates that don't fit into `ADDI`, `LUI` or `QC.LI`
+    // should use `QC.E.LI` (a single 48-bit instruction).
+    if (!FitsOneStandardInst && isInt<32>(Val)) {
+      Res.emplace_back(RISCV::QC_E_LI, Val);
+      return;
+    }
+  }
+
   if (isInt<32>(Val)) {
     // Depending on the active bits in the immediate Value v, the following
     // instruction sequences are emitted:
@@ -523,6 +545,8 @@ OpndKind Inst::getOpndKind() const {
   default:
     llvm_unreachable("Unexpected opcode!");
   case RISCV::LUI:
+  case RISCV::QC_LI:
+  case RISCV::QC_E_LI:
     return RISCVMatInt::Imm;
   case RISCV::ADD_UW:
     return RISCVMatInt::RegX0;

llvm/lib/Target/RISCV/RISCVInstrInfo.cpp

@@ -2603,8 +2603,11 @@ bool RISCVInstrInfo::verifyInstruction(const MachineInstr &MI,
           // clang-format off
         CASE_OPERAND_SIMM(5)
         CASE_OPERAND_SIMM(6)
+        CASE_OPERAND_SIMM(11)
         CASE_OPERAND_SIMM(12)
+        CASE_OPERAND_SIMM(20)
         CASE_OPERAND_SIMM(26)
+        CASE_OPERAND_SIMM(32)
         // clang-format on
         case RISCVOp::OPERAND_SIMM5_PLUS1:
           Ok = (isInt<5>(Imm) && Imm != -16) || Imm == 16;