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[CodeGen] Remove static member function Register::isPhysicalRegister. NFC
Prefer the nonstatic member by converting unsigned to Register instead.
1 parent b0210fe commit 5fadb3d

16 files changed

+32
-39
lines changed

‎llvm/include/llvm/CodeGen/RDFRegisters.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -111,7 +111,7 @@ struct RegisterRef {
111111
}
112112

113113
static constexpr bool isRegId(unsigned Id) {
114-
return Register::isPhysicalRegister(Id);
114+
return Register(Id).isPhysical();
115115
}
116116
static constexpr bool isUnitId(unsigned Id) {
117117
return Register(Id).isVirtual();

‎llvm/include/llvm/CodeGen/Register.h

Lines changed: 3 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -48,12 +48,6 @@ class Register {
4848
return Register(FI + MCRegister::FirstStackSlot);
4949
}
5050

51-
/// Return true if the specified register number is in
52-
/// the physical register namespace.
53-
static constexpr bool isPhysicalRegister(unsigned Reg) {
54-
return MCRegister::isPhysicalRegister(Reg);
55-
}
56-
5751
/// Convert a 0-based index to a virtual register number.
5852
/// This is the inverse operation of VirtReg2IndexFunctor below.
5953
static Register index2VirtReg(unsigned Index) {
@@ -67,7 +61,9 @@ class Register {
6761

6862
/// Return true if the specified register number is in the physical register
6963
/// namespace.
70-
constexpr bool isPhysical() const { return isPhysicalRegister(Reg); }
64+
constexpr bool isPhysical() const {
65+
return MCRegister::isPhysicalRegister(Reg);
66+
}
7167

7268
/// Convert a virtual register number to a 0-based index. The first virtual
7369
/// register in a function will get the index 0.

‎llvm/lib/CodeGen/AsmPrinter/DbgEntityHistoryCalculator.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -525,7 +525,7 @@ void llvm::calculateDbgEntityHistory(const MachineFunction *MF,
525525
// Don't consider SP to be clobbered by register masks.
526526
for (auto It : RegVars) {
527527
unsigned int Reg = It.first;
528-
if (Reg != SP && Register::isPhysicalRegister(Reg) &&
528+
if (Reg != SP && Register(Reg).isPhysical() &&
529529
MO.clobbersPhysReg(Reg))
530530
RegsToClobber.push_back(Reg);
531531
}

‎llvm/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -564,7 +564,7 @@ DIE &DwarfCompileUnit::updateSubprogramScopeDIE(const DISubprogram *SP,
564564
TFI->getDwarfFrameBase(*Asm->MF);
565565
switch (FrameBase.Kind) {
566566
case TargetFrameLowering::DwarfFrameBase::Register: {
567-
if (Register::isPhysicalRegister(FrameBase.Location.Reg)) {
567+
if (Register(FrameBase.Location.Reg).isPhysical()) {
568568
MachineLocation Location(FrameBase.Location.Reg);
569569
addAddress(*SPDie, dwarf::DW_AT_frame_base, Location);
570570
}

‎llvm/lib/CodeGen/LiveRangeCalc.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -216,7 +216,7 @@ bool LiveRangeCalc::findReachingDefs(LiveRange &LR, MachineBasicBlock &UseMBB,
216216
report_fatal_error("Use not jointly dominated by defs.");
217217
}
218218

219-
if (Register::isPhysicalRegister(PhysReg)) {
219+
if (Register(PhysReg).isPhysical()) {
220220
const TargetRegisterInfo *TRI = MRI->getTargetRegisterInfo();
221221
bool IsLiveIn = MBB->isLiveIn(PhysReg);
222222
for (MCRegAliasIterator Alias(PhysReg, TRI, false); !IsLiveIn && Alias.isValid(); ++Alias)

‎llvm/lib/CodeGen/MachineScheduler.cpp

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -3966,8 +3966,7 @@ void GenericScheduler::reschedulePhysReg(SUnit *SU, bool isTop) {
39663966
// Find already scheduled copies with a single physreg dependence and move
39673967
// them just above the scheduled instruction.
39683968
for (SDep &Dep : Deps) {
3969-
if (Dep.getKind() != SDep::Data ||
3970-
!Register::isPhysicalRegister(Dep.getReg()))
3969+
if (Dep.getKind() != SDep::Data || !Register(Dep.getReg()).isPhysical())
39713970
continue;
39723971
SUnit *DepSU = Dep.getSUnit();
39733972
if (isTop ? DepSU->Succs.size() > 1 : DepSU->Preds.size() > 1)

‎llvm/lib/CodeGen/RegAllocFast.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -708,7 +708,7 @@ void RegAllocFastImpl::reloadAtBegin(MachineBasicBlock &MBB) {
708708
/// not used by a virtreg. Kill the physreg, marking it free. This may add
709709
/// implicit kills to MO->getParent() and invalidate MO.
710710
bool RegAllocFastImpl::usePhysReg(MachineInstr &MI, MCPhysReg Reg) {
711-
assert(Register::isPhysicalRegister(Reg) && "expected physreg");
711+
assert(Register(Reg).isPhysical() && "expected physreg");
712712
bool displacedAny = displacePhysReg(MI, Reg);
713713
setPhysRegState(Reg, regPreAssigned);
714714
markRegUsedInInstr(Reg);
@@ -1289,7 +1289,7 @@ void RegAllocFastImpl::dumpState() const {
12891289
assert(VirtReg.isVirtual() && "Bad map key");
12901290
MCPhysReg PhysReg = LR.PhysReg;
12911291
if (PhysReg != 0) {
1292-
assert(Register::isPhysicalRegister(PhysReg) && "mapped to physreg");
1292+
assert(Register(PhysReg).isPhysical() && "mapped to physreg");
12931293
for (MCRegUnit Unit : TRI->regunits(PhysReg)) {
12941294
assert(RegUnitStates[Unit] == VirtReg && "inverse map valid");
12951295
}

‎llvm/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -501,8 +501,8 @@ bool ScheduleDAGFast::DelayForLiveRegsBottomUp(SUnit *SU,
501501
F.isClobberKind()) {
502502
// Check for def of register or earlyclobber register.
503503
for (; NumVals; --NumVals, ++i) {
504-
unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg();
505-
if (Register::isPhysicalRegister(Reg))
504+
Register Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg();
505+
if (Reg.isPhysical())
506506
CheckForLiveRegDef(SU, Reg, LiveRegDefs, RegAdded, LRegs, TRI);
507507
}
508508
} else

‎llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp

Lines changed: 3 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -10125,9 +10125,8 @@ void SelectionDAGBuilder::visitInlineAsm(const CallBase &Call,
1012510125
auto DetectWriteToReservedRegister = [&]() {
1012610126
const MachineFunction &MF = DAG.getMachineFunction();
1012710127
const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
10128-
for (unsigned Reg : OpInfo.AssignedRegs.Regs) {
10129-
if (Register::isPhysicalRegister(Reg) &&
10130-
TRI.isInlineAsmReadOnlyReg(MF, Reg)) {
10128+
for (Register Reg : OpInfo.AssignedRegs.Regs) {
10129+
if (Reg.isPhysical() && TRI.isInlineAsmReadOnlyReg(MF, Reg)) {
1013110130
const char *RegName = TRI.getName(Reg);
1013210131
emitInlineAsmError(Call, "write to reserved register '" +
1013310132
Twine(RegName) + "'");
@@ -11389,7 +11388,7 @@ void SelectionDAGBuilder::CopyValueToVirtualRegister(const Value *V,
1138911388
assert((Op.getOpcode() != ISD::CopyFromReg ||
1139011389
cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) &&
1139111390
"Copy from a reg to the same reg!");
11392-
assert(!Register::isPhysicalRegister(Reg) && "Is a physreg");
11391+
assert(!Register(Reg).isPhysical() && "Is a physreg");
1139311392

1139411393
const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1139511394
// If this is an InlineAsm we have to match the registers required, not the

‎llvm/lib/Target/AArch64/AArch64PBQPRegAlloc.cpp

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -155,11 +155,11 @@ bool A57ChainingConstraint::addIntraChainConstraint(PBQPRAGraph &G, unsigned Rd,
155155

156156
LiveIntervals &LIs = G.getMetadata().LIS;
157157

158-
if (Register::isPhysicalRegister(Rd) || Register::isPhysicalRegister(Ra)) {
159-
LLVM_DEBUG(dbgs() << "Rd is a physical reg:"
160-
<< Register::isPhysicalRegister(Rd) << '\n');
161-
LLVM_DEBUG(dbgs() << "Ra is a physical reg:"
162-
<< Register::isPhysicalRegister(Ra) << '\n');
158+
if (Register(Rd).isPhysical() || Register(Ra).isPhysical()) {
159+
LLVM_DEBUG(dbgs() << "Rd is a physical reg:" << Register(Rd).isPhysical()
160+
<< '\n');
161+
LLVM_DEBUG(dbgs() << "Ra is a physical reg:" << Register(Ra).isPhysical()
162+
<< '\n');
163163
return false;
164164
}
165165

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