Update vector-bo-select.ll

Author: AZero13

llvm/test/CodeGen/X86/vector-bo-select.ll

@@ -2717,6 +2717,100 @@ define <8 x i64> @sub_v8i64_cast_cond(i8 noundef zeroext %pb, <8 x i64> noundef
   ret <8 x i64> %r
 }
 
+define <8 x i64> @sub_v8i64_cast_cond_xor(i8 noundef zeroext %pb, <8 x i64> noundef %x, <8 x i64> noundef %y) {
+; SSE2-LABEL: sub_v8i64_cast_cond_xor:
+; SSE2:       # %bb.0:
+; SSE2-NEXT:    movd %edi, %xmm8
+; SSE2-NEXT:    pshufd {{.*#+}} xmm9 = xmm8[0,1,0,1]
+; SSE2-NEXT:    movdqa {{.*#+}} xmm10 = [64,128]
+; SSE2-NEXT:    movdqa %xmm9, %xmm8
+; SSE2-NEXT:    pand %xmm10, %xmm8
+; SSE2-NEXT:    pcmpeqd %xmm10, %xmm8
+; SSE2-NEXT:    pshufd {{.*#+}} xmm10 = xmm8[1,0,3,2]
+; SSE2-NEXT:    pand %xmm7, %xmm8
+; SSE2-NEXT:    pand %xmm10, %xmm8
+; SSE2-NEXT:    movdqa {{.*#+}} xmm10 = [16,32]
+; SSE2-NEXT:    movdqa %xmm9, %xmm7
+; SSE2-NEXT:    pand %xmm10, %xmm7
+; SSE2-NEXT:    pcmpeqd %xmm10, %xmm7
+; SSE2-NEXT:    pshufd {{.*#+}} xmm10 = xmm7[1,0,3,2]
+; SSE2-NEXT:    pand %xmm6, %xmm7
+; SSE2-NEXT:    pand %xmm10, %xmm7
+; SSE2-NEXT:    movdqa {{.*#+}} xmm6 = [4,8]
+; SSE2-NEXT:    movdqa %xmm9, %xmm10
+; SSE2-NEXT:    pand %xmm6, %xmm10
+; SSE2-NEXT:    pcmpeqd %xmm6, %xmm10
+; SSE2-NEXT:    pshufd {{.*#+}} xmm6 = xmm10[1,0,3,2]
+; SSE2-NEXT:    pand %xmm5, %xmm10
+; SSE2-NEXT:    pand %xmm6, %xmm10
+; SSE2-NEXT:    movdqa {{.*#+}} xmm5 = [1,2]
+; SSE2-NEXT:    pand %xmm5, %xmm9
+; SSE2-NEXT:    pcmpeqd %xmm5, %xmm9
+; SSE2-NEXT:    pshufd {{.*#+}} xmm5 = xmm9[1,0,3,2]
+; SSE2-NEXT:    pand %xmm4, %xmm9
+; SSE2-NEXT:    pand %xmm5, %xmm9
+; SSE2-NEXT:    pxor %xmm9, %xmm0
+; SSE2-NEXT:    pxor %xmm10, %xmm1
+; SSE2-NEXT:    pxor %xmm7, %xmm2
+; SSE2-NEXT:    pxor %xmm8, %xmm3
+; SSE2-NEXT:    retq
+;
+; SSE42-LABEL: sub_v8i64_cast_cond_xor:
+; SSE42:       # %bb.0:
+; SSE42-NEXT:    movd %edi, %xmm8
+; SSE42-NEXT:    pshufd {{.*#+}} xmm9 = xmm8[0,1,0,1]
+; SSE42-NEXT:    pmovzxbq {{.*#+}} xmm10 = [64,128]
+; SSE42-NEXT:    movdqa %xmm9, %xmm8
+; SSE42-NEXT:    pand %xmm10, %xmm8
+; SSE42-NEXT:    pcmpeqq %xmm10, %xmm8
+; SSE42-NEXT:    pand %xmm7, %xmm8
+; SSE42-NEXT:    pmovsxbq {{.*#+}} xmm7 = [16,32]
+; SSE42-NEXT:    movdqa %xmm9, %xmm10
+; SSE42-NEXT:    pand %xmm7, %xmm10
+; SSE42-NEXT:    pcmpeqq %xmm7, %xmm10
+; SSE42-NEXT:    pand %xmm6, %xmm10
+; SSE42-NEXT:    pmovsxbq {{.*#+}} xmm6 = [4,8]
+; SSE42-NEXT:    movdqa %xmm9, %xmm7
+; SSE42-NEXT:    pand %xmm6, %xmm7
+; SSE42-NEXT:    pcmpeqq %xmm6, %xmm7
+; SSE42-NEXT:    pand %xmm5, %xmm7
+; SSE42-NEXT:    pmovsxbq {{.*#+}} xmm5 = [1,2]
+; SSE42-NEXT:    pand %xmm5, %xmm9
+; SSE42-NEXT:    pcmpeqq %xmm5, %xmm9
+; SSE42-NEXT:    pand %xmm4, %xmm9
+; SSE42-NEXT:    pxor %xmm9, %xmm0
+; SSE42-NEXT:    pxor %xmm7, %xmm1
+; SSE42-NEXT:    pxor %xmm10, %xmm2
+; SSE42-NEXT:    pxor %xmm8, %xmm3
+; SSE42-NEXT:    retq
+;
+; AVX2-LABEL: sub_v8i64_cast_cond_xor:
+; AVX2:       # %bb.0:
+; AVX2-NEXT:    vmovd %edi, %xmm4
+; AVX2-NEXT:    vpbroadcastb %xmm4, %ymm4
+; AVX2-NEXT:    vpmovzxbq {{.*#+}} ymm5 = [16,32,64,128]
+; AVX2-NEXT:    vpand %ymm5, %ymm4, %ymm6
+; AVX2-NEXT:    vpcmpeqq %ymm5, %ymm6, %ymm5
+; AVX2-NEXT:    vpand %ymm3, %ymm5, %ymm3
+; AVX2-NEXT:    vpmovsxbq {{.*#+}} ymm5 = [1,2,4,8]
+; AVX2-NEXT:    vpand %ymm5, %ymm4, %ymm4
+; AVX2-NEXT:    vpcmpeqq %ymm5, %ymm4, %ymm4
+; AVX2-NEXT:    vpand %ymm2, %ymm4, %ymm2
+; AVX2-NEXT:    vpxor %ymm2, %ymm0, %ymm0
+; AVX2-NEXT:    vpxor %ymm3, %ymm1, %ymm1
+; AVX2-NEXT:    retq
+;
+; AVX512-LABEL: sub_v8i64_cast_cond_xor:
+; AVX512:       # %bb.0:
+; AVX512-NEXT:    kmovw %edi, %k1
+; AVX512-NEXT:    vpxorq %zmm1, %zmm0, %zmm0 {%k1}
+; AVX512-NEXT:    retq
+  %b = bitcast i8 %pb to <8 x i1>
+  %s = select <8 x i1> %b, <8 x i64> %y, <8 x i64> zeroinitializer
+  %r = xor <8 x i64> %x, %s
+  ret <8 x i64> %r
+}
+
 define <4 x i32> @mul_v4i32(<4 x i1> %b, <4 x i32> noundef %x, <4 x i32> noundef %y) {
 ; SSE2-LABEL: mul_v4i32:
 ; SSE2:       # %bb.0: