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4vtomat4vtomat
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fixup! Remove command line option
1 parent 8c8ef94 commit 5190e0f

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10 files changed

+25
-89
lines changed

10 files changed

+25
-89
lines changed

‎clang/include/clang/Basic/CodeGenOptions.def

Lines changed: 0 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -465,9 +465,6 @@ ENUM_CODEGENOPT(ZeroCallUsedRegs, llvm::ZeroCallUsedRegs::ZeroCallUsedRegsKind,
465465
/// non-deleting destructors. (No effect on Microsoft ABI.)
466466
CODEGENOPT(CtorDtorReturnThis, 1, 0)
467467

468-
/// Specify the VLEN for VLS calling convention.
469-
CODEGENOPT(RISCVABIVLen, 17, 0)
470-
471468
/// FIXME: Make DebugOptions its own top-level .def file.
472469
#include "DebugOptions.def"
473470

‎clang/include/clang/Driver/Options.td

Lines changed: 0 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -4992,10 +4992,6 @@ def mrvv_vector_bits_EQ : Joined<["-"], "mrvv-vector-bits=">, Group<m_Group>,
49924992
!eq(GlobalDocumentation.Program, "Flang") : "",
49934993
true: " The value will be reflected in __riscv_v_fixed_vlen preprocessor define"),
49944994
" (RISC-V only)")>;
4995-
def mriscv_abi_vlen_EQ : Joined<["-"], "mriscv-abi-vlen=">, Group<m_Group>,
4996-
Visibility<[ClangOption, CC1Option]>,
4997-
HelpText<"Specify the VLEN for VLS calling convention.">,
4998-
MarshallingInfoInt<CodeGenOpts<"RISCVABIVLen">>;
49994995
def munaligned_access : Flag<["-"], "munaligned-access">, Group<m_Group>,
50004996
HelpText<"Allow memory accesses to be unaligned (AArch32/MIPSr6 only)">;
50014997
def mno_unaligned_access : Flag<["-"], "mno-unaligned-access">, Group<m_Group>,

‎clang/lib/CodeGen/CodeGenModule.cpp

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -231,8 +231,7 @@ createTargetCodeGenInfo(CodeGenModule &CGM) {
231231
else if (ABIStr.ends_with("d"))
232232
ABIFLen = 64;
233233
bool EABI = ABIStr.ends_with("e");
234-
return createRISCVTargetCodeGenInfo(CGM, XLen, ABIFLen,
235-
CodeGenOpts.RISCVABIVLen, EABI);
234+
return createRISCVTargetCodeGenInfo(CGM, XLen, ABIFLen, EABI);
236235
}
237236

238237
case llvm::Triple::systemz: {

‎clang/lib/CodeGen/TargetInfo.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -551,7 +551,7 @@ createPPC64_SVR4_TargetCodeGenInfo(CodeGenModule &CGM, PPC64_SVR4_ABIKind Kind,
551551

552552
std::unique_ptr<TargetCodeGenInfo>
553553
createRISCVTargetCodeGenInfo(CodeGenModule &CGM, unsigned XLen, unsigned FLen,
554-
unsigned ABIVLen, bool EABI);
554+
bool EABI);
555555

556556
std::unique_ptr<TargetCodeGenInfo>
557557
createCommonSPIRTargetCodeGenInfo(CodeGenModule &CGM);

‎clang/lib/CodeGen/Targets/RISCV.cpp

Lines changed: 20 additions & 30 deletions
Original file line numberDiff line numberDiff line change
@@ -26,7 +26,6 @@ class RISCVABIInfo : public DefaultABIInfo {
2626
// ISA might have a wider FLen than the selected ABI (e.g. an RV32IF target
2727
// with soft float ABI has FLen==0).
2828
unsigned FLen;
29-
unsigned ABIVLen;
3029
const int NumArgGPRs;
3130
const int NumArgFPRs;
3231
const bool EABI;
@@ -38,17 +37,17 @@ class RISCVABIInfo : public DefaultABIInfo {
3837

3938
public:
4039
RISCVABIInfo(CodeGen::CodeGenTypes &CGT, unsigned XLen, unsigned FLen,
41-
unsigned ABIVLen, bool EABI)
42-
: DefaultABIInfo(CGT), XLen(XLen), FLen(FLen), ABIVLen(ABIVLen),
40+
bool EABI)
41+
: DefaultABIInfo(CGT), XLen(XLen), FLen(FLen),
4342
NumArgGPRs(EABI ? 6 : 8), NumArgFPRs(FLen != 0 ? 8 : 0), EABI(EABI) {}
4443

4544
// DefaultABIInfo's classifyReturnType and classifyArgumentType are
4645
// non-virtual, but computeInfo is virtual, so we overload it.
4746
void computeInfo(CGFunctionInfo &FI) const override;
4847

4948
ABIArgInfo classifyArgumentType(QualType Ty, bool IsFixed, int &ArgGPRsLeft,
50-
int &ArgFPRsLeft, unsigned ArgABIVLen) const;
51-
ABIArgInfo classifyReturnType(QualType RetTy, unsigned ArgABIVLen) const;
49+
int &ArgFPRsLeft, unsigned ABIVLen) const;
50+
ABIArgInfo classifyReturnType(QualType RetTy, unsigned ABIVLen) const;
5251

5352
RValue EmitVAArg(CodeGenFunction &CGF, Address VAListAddr, QualType Ty,
5453
AggValueSlot Slot) const override;
@@ -64,7 +63,7 @@ class RISCVABIInfo : public DefaultABIInfo {
6463
llvm::Type *Field2Ty,
6564
CharUnits Field2Off) const;
6665

67-
ABIArgInfo coerceVLSVector(QualType Ty, unsigned ArgABIVLen = 0) const;
66+
ABIArgInfo coerceVLSVector(QualType Ty, unsigned ABIVLen = 0) const;
6867

6968
using ABIInfo::appendAttributeMangling;
7069
void appendAttributeMangling(TargetClonesAttr *Attr, unsigned Index,
@@ -113,18 +112,10 @@ void RISCVABIInfo::appendAttributeMangling(StringRef AttrStr,
113112
}
114113

115114
void RISCVABIInfo::computeInfo(CGFunctionInfo &FI) const {
116-
unsigned ArgABIVLen = 1 << FI.getExtInfo().getLog2RISCVABIVLen();
117-
// If ArgABIVLen is default value(2), try to set it to the value passed by
118-
// option if any, otherwise, set it to default value 128.
119-
// Note that ArgABIVLen == 1 means vector_cc is not enabled.
120-
if (ArgABIVLen == 2 && ABIVLen)
121-
ArgABIVLen = ABIVLen;
122-
else if (ArgABIVLen == 2)
123-
ArgABIVLen = 128;
124-
115+
unsigned ABIVLen = 1 << FI.getExtInfo().getLog2RISCVABIVLen();
125116
QualType RetTy = FI.getReturnType();
126117
if (!getCXXABI().classifyReturnType(FI))
127-
FI.getReturnInfo() = classifyReturnType(RetTy, ArgABIVLen);
118+
FI.getReturnInfo() = classifyReturnType(RetTy, ABIVLen);
128119

129120
// IsRetIndirect is true if classifyArgumentType indicated the value should
130121
// be passed indirect, or if the type size is a scalar greater than 2*XLen
@@ -151,7 +142,7 @@ void RISCVABIInfo::computeInfo(CGFunctionInfo &FI) const {
151142
for (auto &ArgInfo : FI.arguments()) {
152143
bool IsFixed = ArgNum < NumFixedArgs;
153144
ArgInfo.info = classifyArgumentType(ArgInfo.type, IsFixed, ArgGPRsLeft,
154-
ArgFPRsLeft, ArgABIVLen);
145+
ArgFPRsLeft, ABIVLen);
155146
ArgNum++;
156147
}
157148
}
@@ -373,7 +364,7 @@ ABIArgInfo RISCVABIInfo::coerceAndExpandFPCCEligibleStruct(
373364
// Fixed-length RVV vectors are represented as scalable vectors in function
374365
// args/return and must be coerced from fixed vectors.
375366
ABIArgInfo RISCVABIInfo::coerceVLSVector(QualType Ty,
376-
unsigned ArgABIVLen) const {
367+
unsigned ABIVLen) const {
377368
assert(Ty->isVectorType() && "expected vector type!");
378369

379370
const auto *VT = Ty->castAs<VectorType>();
@@ -405,7 +396,7 @@ ABIArgInfo RISCVABIInfo::coerceVLSVector(QualType Ty,
405396

406397
llvm::ScalableVectorType *ResType;
407398

408-
if (ArgABIVLen == 0) {
399+
if (ABIVLen == 0) {
409400
// The MinNumElts is simplified from equation:
410401
// NumElts / VScale =
411402
// (EltSize * NumElts / (VScale * RVVBitsPerBlock))
@@ -429,7 +420,7 @@ ABIArgInfo RISCVABIInfo::coerceVLSVector(QualType Ty,
429420
// The number of elements needs to be at least 1.
430421
ResType = llvm::ScalableVectorType::get(
431422
EltType,
432-
llvm::divideCeil(NumElts * llvm::RISCV::RVVBitsPerBlock, ArgABIVLen));
423+
llvm::divideCeil(NumElts * llvm::RISCV::RVVBitsPerBlock, ABIVLen));
433424
}
434425

435426
return ABIArgInfo::getDirect(ResType);
@@ -438,7 +429,7 @@ ABIArgInfo RISCVABIInfo::coerceVLSVector(QualType Ty,
438429
ABIArgInfo RISCVABIInfo::classifyArgumentType(QualType Ty, bool IsFixed,
439430
int &ArgGPRsLeft,
440431
int &ArgFPRsLeft,
441-
unsigned ArgABIVLen) const {
432+
unsigned ABIVLen) const {
442433
assert(ArgGPRsLeft <= NumArgGPRs && "Arg GPR tracking underflow");
443434
Ty = useFirstFieldIfTransparentUnion(Ty);
444435

@@ -542,10 +533,10 @@ ABIArgInfo RISCVABIInfo::classifyArgumentType(QualType Ty, bool IsFixed,
542533
VT->getVectorKind() == VectorKind::RVVFixedLengthMask_2 ||
543534
VT->getVectorKind() == VectorKind::RVVFixedLengthMask_4)
544535
return coerceVLSVector(Ty);
545-
if (VT->getVectorKind() == VectorKind::Generic && ArgABIVLen != 1)
536+
if (VT->getVectorKind() == VectorKind::Generic && ABIVLen != 1)
546537
// Generic vector without riscv_vls_cc should fall through and pass by
547538
// reference.
548-
return coerceVLSVector(Ty, ArgABIVLen);
539+
return coerceVLSVector(Ty, ABIVLen);
549540
}
550541

551542
// Aggregates which are <= 2*XLen will be passed in registers if possible,
@@ -570,7 +561,7 @@ ABIArgInfo RISCVABIInfo::classifyArgumentType(QualType Ty, bool IsFixed,
570561
}
571562

572563
ABIArgInfo RISCVABIInfo::classifyReturnType(QualType RetTy,
573-
unsigned ArgABIVLen) const {
564+
unsigned ABIVLen) const {
574565
if (RetTy->isVoidType())
575566
return ABIArgInfo::getIgnore();
576567

@@ -580,7 +571,7 @@ ABIArgInfo RISCVABIInfo::classifyReturnType(QualType RetTy,
580571
// The rules for return and argument types are the same, so defer to
581572
// classifyArgumentType.
582573
return classifyArgumentType(RetTy, /*IsFixed=*/true, ArgGPRsLeft, ArgFPRsLeft,
583-
ArgABIVLen);
574+
ABIVLen);
584575
}
585576

586577
RValue RISCVABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
@@ -619,9 +610,9 @@ namespace {
619610
class RISCVTargetCodeGenInfo : public TargetCodeGenInfo {
620611
public:
621612
RISCVTargetCodeGenInfo(CodeGen::CodeGenTypes &CGT, unsigned XLen,
622-
unsigned FLen, unsigned ABIVLen, bool EABI)
613+
unsigned FLen, bool EABI)
623614
: TargetCodeGenInfo(
624-
std::make_unique<RISCVABIInfo>(CGT, XLen, FLen, ABIVLen, EABI)) {
615+
std::make_unique<RISCVABIInfo>(CGT, XLen, FLen, EABI)) {
625616
SwiftInfo =
626617
std::make_unique<SwiftABIInfo>(CGT, /*SwiftErrorInRegister=*/false);
627618
}
@@ -653,8 +644,7 @@ class RISCVTargetCodeGenInfo : public TargetCodeGenInfo {
653644

654645
std::unique_ptr<TargetCodeGenInfo>
655646
CodeGen::createRISCVTargetCodeGenInfo(CodeGenModule &CGM, unsigned XLen,
656-
unsigned FLen, unsigned ABIVLen,
657-
bool EABI) {
647+
unsigned FLen, bool EABI) {
658648
return std::make_unique<RISCVTargetCodeGenInfo>(CGM.getTypes(), XLen, FLen,
659-
ABIVLen, EABI);
649+
EABI);
660650
}

‎clang/lib/Driver/ToolChains/Arch/RISCV.cpp

Lines changed: 0 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -95,10 +95,6 @@ void riscv::getRISCVTargetFeatures(const Driver &D, const llvm::Triple &Triple,
9595
CPUFastVectorUnaligned = true;
9696
}
9797

98-
if (Arg *A = Args.getLastArg(options::OPT_mriscv_abi_vlen_EQ))
99-
Features.push_back(
100-
Args.MakeArgString(Twine("+abi-vlen-") + A->getValue() + "b"));
101-
10298
// Handle features corresponding to "-ffixed-X" options
10399
#define RESERVE_REG(REG) \
104100
if (Args.hasArg(options::OPT_ffixed_##REG)) \

‎clang/lib/Driver/ToolChains/Clang.cpp

Lines changed: 0 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -2225,21 +2225,6 @@ void Clang::AddRISCVTargetArgs(const ArgList &Args,
22252225
<< A->getSpelling() << Val;
22262226
}
22272227
}
2228-
2229-
if (Arg *A = Args.getLastArg(options::OPT_mriscv_abi_vlen_EQ)) {
2230-
StringRef ABIVLenStr = A->getValue();
2231-
unsigned ABIVLen;
2232-
const Driver &D = getToolChain().getDriver();
2233-
if (ABIVLenStr.getAsInteger(10, ABIVLen) || ABIVLen < 32 ||
2234-
ABIVLen > 65536 || !llvm::isPowerOf2_64(ABIVLen)) {
2235-
D.Diag(diag::err_drv_invalid_value)
2236-
<< A->getOption().getName() << ABIVLenStr;
2237-
return;
2238-
}
2239-
2240-
CmdArgs.push_back(
2241-
Args.MakeArgString(Twine("-mriscv-abi-vlen=") + A->getValue()));
2242-
}
22432228
}
22442229

22452230
void Clang::AddSparcTargetArgs(const ArgList &Args,

‎clang/lib/Sema/SemaType.cpp

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -8107,9 +8107,9 @@ static bool handleFunctionTypeAttr(TypeProcessingState &state, ParsedAttr &attr,
81078107
Attr *CCAttr = getCCTypeAttr(S.Context, attr);
81088108

81098109
if (attr.getKind() == ParsedAttr::AT_RISCVVLSCC) {
8110-
// If the riscv_abi_vlen doesn't have any argument, we set set it to 2 to
8111-
// differentiate from functions without attribute.
8112-
unsigned ABIVLen = 2;
8110+
// If the riscv_abi_vlen doesn't have any argument, we set set it to default
8111+
// value 128.
8112+
unsigned ABIVLen = 128;
81138113
if (attr.getNumArgs() &&
81148114
!S.checkUInt32Argument(attr, attr.getArgAsExpr(0), ABIVLen))
81158115
return false;

‎clang/test/CodeGen/RISCV/riscv-vector-callingconv-llvm-ir.c

Lines changed: 0 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -5,12 +5,6 @@
55
// RUN: -emit-llvm %s -o - | FileCheck -check-prefix=CHECK-LLVM-ZVE32X %s
66
// RUN: %clang_cc1 -std=c23 -triple riscv64 -target-feature +v \
77
// RUN: -emit-llvm %s -o - | FileCheck -check-prefix=CHECK-LLVM %s
8-
// RUN: %clang_cc1 -triple riscv64 -mriscv-abi-vlen=256 -target-feature +v \
9-
// RUN: -emit-llvm %s -o - | FileCheck -check-prefix=CHECK-LLVM-ABI-VLEN %s
10-
// RUN: %clang_cc1 -triple riscv64 -mriscv-abi-vlen=256 -target-feature +zve32x \
11-
// RUN: -emit-llvm %s -o - | FileCheck -check-prefix=CHECK-LLVM-ABI-VLEN-ZVE32X %s
12-
// RUN: %clang_cc1 -std=c23 -triple riscv64 -mriscv-abi-vlen=256 -target-feature +v \
13-
// RUN: -emit-llvm %s -o - | FileCheck -check-prefix=CHECK-LLVM-ABI-VLEN %s
148

159
#include <riscv_vector.h>
1610

@@ -42,45 +36,34 @@ vint32m1_t test_no_vector_cc_attr(vint32m1_t input, int32_t *base, size_t vl) {
4236
}
4337

4438
// CHECK-LLVM: define dso_local void @test_vls_no_cc(i128 noundef %arg.coerce)
45-
// CHECK-LLVM-ABI-VLEN: define dso_local void @test_vls_no_cc(i128 noundef %arg.coerce)
4639
void test_vls_no_cc(__attribute__((vector_size(16))) int arg) {}
4740

4841
// CHECK-LLVM: define dso_local riscv_vls_cc void @test_vls_default_abi_vlen(<vscale x 2 x i32> noundef %arg.coerce)
49-
// CHECK-LLVM-ABI-VLEN: define dso_local riscv_vls_cc void @test_vls_default_abi_vlen(<vscale x 1 x i32> noundef %arg.coerce)
5042
void __attribute__((riscv_vls_cc)) test_vls_default_abi_vlen(__attribute__((vector_size(16))) int arg) {}
5143

5244
// CHECK-LLVM: define dso_local riscv_vls_cc void @test_vls_default_abi_vlen_c23(<vscale x 2 x i32> noundef %arg.coerce)
53-
// CHECK-LLVM-ABI-VLEN: define dso_local riscv_vls_cc void @test_vls_default_abi_vlen_c23(<vscale x 1 x i32> noundef %arg.coerce)
5445
[[riscv::vls_cc]] void test_vls_default_abi_vlen_c23(__attribute__((vector_size(16))) int arg) {}
5546

5647
// CHECK-LLVM: define dso_local riscv_vls_cc void @test_vls_default_abi_vlen_unsupported_feature(<vscale x 4 x i16> noundef %arg.coerce)
57-
// CHECK-LLVM-ABI-VLEN: define dso_local riscv_vls_cc void @test_vls_default_abi_vlen_unsupported_feature(<vscale x 2 x i16> noundef %arg.coerce)
5848
void __attribute__((riscv_vls_cc)) test_vls_default_abi_vlen_unsupported_feature(__attribute__((vector_size(16))) _Float16 arg) {}
5949

6050
// CHECK-LLVM: define dso_local riscv_vls_cc void @test_vls_default_abi_vlen_c23_unsupported_feature(<vscale x 4 x i16> noundef %arg.coerce)
61-
// CHECK-LLVM-ABI-VLEN: define dso_local riscv_vls_cc void @test_vls_default_abi_vlen_c23_unsupported_feature(<vscale x 2 x i16> noundef %arg.coerce)
6251
[[riscv::vls_cc]] void test_vls_default_abi_vlen_c23_unsupported_feature(__attribute__((vector_size(16))) _Float16 arg) {}
6352

6453
// CHECK-LLVM-ZVE32X: define dso_local riscv_vls_cc void @test_vls_default_abi_vlen_unsupported_feature_zve32x(<vscale x 2 x i32> noundef %arg.coerce)
65-
// CHECK-LLVM-ABI-VLEN-ZVE32X: define dso_local riscv_vls_cc void @test_vls_default_abi_vlen_unsupported_feature_zve32x(<vscale x 1 x i32> noundef %arg.coerce)
6654
void __attribute__((riscv_vls_cc)) test_vls_default_abi_vlen_unsupported_feature_zve32x(__attribute__((vector_size(16))) float arg) {}
6755

6856
// CHECK-LLVM-ZVE32X: define dso_local riscv_vls_cc void @test_vls_default_abi_vlen_c23_unsupported_feature_zve32x(<vscale x 2 x i32> noundef %arg.coerce)
69-
// CHECK-LLVM-ABI-VLEN-ZVE32X: define dso_local riscv_vls_cc void @test_vls_default_abi_vlen_c23_unsupported_feature_zve32x(<vscale x 1 x i32> noundef %arg.coerce)
7057
[[riscv::vls_cc]] void test_vls_default_abi_vlen_c23_unsupported_feature_zve32x(__attribute__((vector_size(16))) float arg) {}
7158

7259
// CHECK-LLVM: define dso_local riscv_vls_cc void @test_vls_256_abi_vlen(<vscale x 1 x i32> noundef %arg.coerce)
73-
// CHECK-LLVM-ABI-VLEN: define dso_local riscv_vls_cc void @test_vls_256_abi_vlen(<vscale x 1 x i32> noundef %arg.coerce)
7460
void __attribute__((riscv_vls_cc(256))) test_vls_256_abi_vlen(__attribute__((vector_size(16))) int arg) {}
7561

7662
// CHECK-LLVM: define dso_local riscv_vls_cc void @test_vls_256_abi_vlen_c23(<vscale x 1 x i32> noundef %arg.coerce)
77-
// CHECK-LLVM-ABI-VLEN: define dso_local riscv_vls_cc void @test_vls_256_abi_vlen_c23(<vscale x 1 x i32> noundef %arg.coerce)
7863
[[riscv::vls_cc(256)]] void test_vls_256_abi_vlen_c23(__attribute__((vector_size(16))) int arg) {}
7964

8065
// CHECK-LLVM: define dso_local riscv_vls_cc void @test_vls_least_element(<vscale x 1 x i32> noundef %arg.coerce)
81-
// CHECK-LLVM-ABI-VLEN: define dso_local riscv_vls_cc void @test_vls_least_element(<vscale x 1 x i32> noundef %arg.coerce)
8266
void __attribute__((riscv_vls_cc(1024))) test_vls_least_element(__attribute__((vector_size(8))) int arg) {}
8367

8468
// CHECK-LLVM: define dso_local riscv_vls_cc void @test_vls_least_element_c23(<vscale x 1 x i32> noundef %arg.coerce)
85-
// CHECK-LLVM-ABI-VLEN: define dso_local riscv_vls_cc void @test_vls_least_element_c23(<vscale x 1 x i32> noundef %arg.coerce)
8669
[[riscv::vls_cc(1024)]] void test_vls_least_element_c23(__attribute__((vector_size(8))) int arg) {}

‎clang/test/CodeGen/RISCV/riscv-vector-callingconv-llvm-ir.cpp

Lines changed: 0 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -3,10 +3,6 @@
33
// RUN: -emit-llvm %s -o - | FileCheck -check-prefix=CHECK-LLVM %s
44
// RUN: %clang_cc1 -std=c++11 -triple riscv64 -target-feature +zve32x \
55
// RUN: -emit-llvm %s -o - | FileCheck -check-prefix=CHECK-LLVM-ZVE32X %s
6-
// RUN: %clang_cc1 -std=c++11 -triple riscv64 -mriscv-abi-vlen=256 -target-feature +v \
7-
// RUN: -emit-llvm %s -o - | FileCheck -check-prefix=CHECK-LLVM-ABI-VLEN %s
8-
// RUN: %clang_cc1 -std=c++11 -triple riscv64 -mriscv-abi-vlen=256 -target-feature +zve32x \
9-
// RUN: -emit-llvm %s -o - | FileCheck -check-prefix=CHECK-LLVM-ABI-VLEN-ZVE32X %s
106

117
#include <riscv_vector.h>
128

@@ -38,25 +34,19 @@ vint32m1_t test_no_vector_cc_attr(vint32m1_t input, int32_t *base, size_t vl) {
3834
}
3935

4036
// CHECK-LLVM: define dso_local void @_Z14test_vls_no_ccDv4_i(i128 noundef %arg.coerce)
41-
// CHECK-LLVM-ABI-VLEN: define dso_local void @_Z14test_vls_no_ccDv4_i(i128 noundef %arg.coerce)
4237
void test_vls_no_cc(__attribute__((vector_size(16))) int arg) {}
4338

4439
// CHECK-LLVM: define dso_local riscv_vls_cc void @_Z25test_vls_default_abi_vlenDv4_i(<vscale x 2 x i32> noundef %arg.coerce)
45-
// CHECK-LLVM-ABI-VLEN: define dso_local riscv_vls_cc void @_Z25test_vls_default_abi_vlenDv4_i(<vscale x 1 x i32> noundef %arg.coerce)
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[[riscv::vls_cc]] void test_vls_default_abi_vlen(__attribute__((vector_size(16))) int arg) {}
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// CHECK-LLVM: define dso_local riscv_vls_cc void @_Z45test_vls_default_abi_vlen_unsupported_featureDv8_DF16_(<vscale x 4 x i16> noundef %arg.coerce)
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// CHECK-LLVM-ABI-VLEN: define dso_local riscv_vls_cc void @_Z45test_vls_default_abi_vlen_unsupported_featureDv8_DF16_(<vscale x 2 x i16> noundef %arg.coerce)
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[[riscv::vls_cc]] void test_vls_default_abi_vlen_unsupported_feature(__attribute__((vector_size(16))) _Float16 arg) {}
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// CHECK-LLVM-ZVE32X: define dso_local riscv_vls_cc void @_Z52test_vls_default_abi_vlen_unsupported_feature_zve32xDv4_f(<vscale x 2 x i32> noundef %arg.coerce)
53-
// CHECK-LLVM-ABI-VLEN-ZVE32X: define dso_local riscv_vls_cc void @_Z52test_vls_default_abi_vlen_unsupported_feature_zve32xDv4_f(<vscale x 1 x i32> noundef %arg.coerce)
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[[riscv::vls_cc]] void test_vls_default_abi_vlen_unsupported_feature_zve32x(__attribute__((vector_size(16))) float arg) {}
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// CHECK-LLVM: define dso_local riscv_vls_cc void @_Z21test_vls_256_abi_vlenDv4_i(<vscale x 1 x i32> noundef %arg.coerce)
57-
// CHECK-LLVM-ABI-VLEN: define dso_local riscv_vls_cc void @_Z21test_vls_256_abi_vlenDv4_i(<vscale x 1 x i32> noundef %arg.coerce)
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[[riscv::vls_cc(256)]] void test_vls_256_abi_vlen(__attribute__((vector_size(16))) int arg) {}
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// CHECK-LLVM: define dso_local riscv_vls_cc void @_Z22test_vls_least_elementDv2_i(<vscale x 1 x i32> noundef %arg.coerce)
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// CHECK-LLVM-ABI-VLEN: define dso_local riscv_vls_cc void @_Z22test_vls_least_elementDv2_i(<vscale x 1 x i32> noundef %arg.coerce)
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[[riscv::vls_cc(1024)]] void test_vls_least_element(__attribute__((vector_size(8))) int arg) {}

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