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llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

Lines changed: 22 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -15136,21 +15136,31 @@ SDValue DAGCombiner::visitAssertExt(SDNode *N) {
1513615136
}
1513715137
}
1513815138

15139-
// If we have (AssertZext (and (AssertSext X, iX), M), iY) and Y is smaller
15140-
// than X, and the And doesn't change the lower iX bits, we can move the
15141-
// AssertZext in front of the And and drop the AssertSext.
1514215139
if (Opcode == ISD::AssertZext && N0.getOpcode() == ISD::AND &&
15143-
N0.hasOneUse() && N0.getOperand(0).getOpcode() == ISD::AssertSext &&
15144-
isa<ConstantSDNode>(N0.getOperand(1))) {
15145-
SDValue BigA = N0.getOperand(0);
15146-
EVT BigA_AssertVT = cast<VTSDNode>(BigA.getOperand(1))->getVT();
15140+
N0.hasOneUse() && isa<ConstantSDNode>(N0.getOperand(1))) {
1514715141
const APInt &Mask = N0.getConstantOperandAPInt(1);
15148-
if (AssertVT.bitsLT(BigA_AssertVT) &&
15149-
Mask.countr_one() >= BigA_AssertVT.getScalarSizeInBits()) {
15142+
15143+
// If we have (AssertZext (and (AssertSext X, iX), M), iY) and Y is smaller
15144+
// than X, and the And doesn't change the lower iX bits, we can move the
15145+
// AssertZext in front of the And and drop the AssertSext.
15146+
if (N0.getOperand(0).getOpcode() == ISD::AssertSext) {
15147+
SDValue BigA = N0.getOperand(0);
15148+
EVT BigA_AssertVT = cast<VTSDNode>(BigA.getOperand(1))->getVT();
15149+
if (AssertVT.bitsLT(BigA_AssertVT) &&
15150+
Mask.countr_one() >= BigA_AssertVT.getScalarSizeInBits()) {
15151+
SDLoc DL(N);
15152+
SDValue NewAssert =
15153+
DAG.getNode(Opcode, DL, N->getValueType(0), BigA.getOperand(0), N1);
15154+
return DAG.getNode(ISD::AND, DL, N->getValueType(0), NewAssert,
15155+
N0.getOperand(1));
15156+
}
15157+
}
15158+
15159+
// Remove AssertZext entirely if the mask guarantees the assertion cannot
15160+
// fail.
15161+
if (Mask.isMask() && Mask.countr_one() <= AssertVT.getScalarSizeInBits()) {
1515015162
SDLoc DL(N);
15151-
SDValue NewAssert =
15152-
DAG.getNode(Opcode, DL, N->getValueType(0), BigA.getOperand(0), N1);
15153-
return DAG.getNode(ISD::AND, DL, N->getValueType(0), NewAssert,
15163+
return DAG.getNode(ISD::AND, DL, N0.getValueType(), N0.getOperand(0),
1515415164
N0.getOperand(1));
1515515165
}
1515615166
}

llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp

Lines changed: 0 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -3985,24 +3985,6 @@ SDValue AMDGPUTargetLowering::performAssertSZExtCombine(SDNode *N,
39853985
}
39863986
}
39873987

3988-
// AssertZext in front of these intrinsics is not necessary, the lowering of
3989-
// the intrinsics into a register read will insert one if it is needed.
3990-
if (N->getOpcode() == ISD::AssertZext &&
3991-
N0.getOpcode() == ISD::INTRINSIC_WO_CHAIN) {
3992-
unsigned IID = N0.getConstantOperandVal(0);
3993-
switch (IID) {
3994-
case Intrinsic::amdgcn_workitem_id_x:
3995-
case Intrinsic::amdgcn_workitem_id_y:
3996-
case Intrinsic::amdgcn_workitem_id_z:
3997-
case Intrinsic::amdgcn_workgroup_id_x:
3998-
case Intrinsic::amdgcn_workgroup_id_y:
3999-
case Intrinsic::amdgcn_workgroup_id_z:
4000-
return N0;
4001-
default:
4002-
break;
4003-
}
4004-
}
4005-
40063988
return SDValue();
40073989
}
40083990

llvm/test/CodeGen/AMDGPU/llvm.amdgcn.workitem.id-unsupported-calling-convention.ll

Lines changed: 11 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -9,9 +9,16 @@ declare i32 @llvm.amdgcn.workitem.id.z()
99
; FIXME: It's not worth adding AssertZext to the intrinsic calls, and
1010
; we don't fold out assertzext undef ->undef
1111
define amdgpu_ps void @undefined_workitems(ptr addrspace(1) %p, ptr addrspace(1) %q, ptr addrspace(1) %r) {
12-
; CHECK-LABEL: undefined_workitems:
13-
; CHECK: ; %bb.0:
14-
; CHECK-NEXT: s_endpgm
12+
; SDAG-LABEL: undefined_workitems:
13+
; SDAG: ; %bb.0:
14+
; SDAG-NEXT: global_store_dword v[0:1], v0, off
15+
; SDAG-NEXT: global_store_dword v[2:3], v0, off
16+
; SDAG-NEXT: global_store_dword v[4:5], v0, off
17+
; SDAG-NEXT: s_endpgm
18+
;
19+
; GISEL-LABEL: undefined_workitems:
20+
; GISEL: ; %bb.0:
21+
; GISEL-NEXT: s_endpgm
1522
%id.x = call i32 @llvm.amdgcn.workitem.id.x()
1623
store i32 %id.x, ptr addrspace(1) %p
1724
%id.y = call i32 @llvm.amdgcn.workitem.id.y()
@@ -21,5 +28,4 @@ define amdgpu_ps void @undefined_workitems(ptr addrspace(1) %p, ptr addrspace(1)
2128
ret void
2229
}
2330
;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
24-
; GISEL: {{.*}}
25-
; SDAG: {{.*}}
31+
; CHECK: {{.*}}

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