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[TableGen] Use emplace instead of insert and similar. NFC. (#143164)
1 parent bb9dcb2 commit 432c5f2

11 files changed

+31
-28
lines changed

‎llvm/utils/TableGen/AsmWriterEmitter.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1138,10 +1138,10 @@ void AsmWriterEmitter::EmitPrintAliasInstruction(raw_ostream &O) {
11381138
uint32_t UnescapedSize = 0;
11391139
std::string EncodedAsmString = IAP->formatAliasString(UnescapedSize);
11401140
auto Insertion =
1141-
AsmStringOffsets.insert({EncodedAsmString, AsmStringsSize});
1141+
AsmStringOffsets.try_emplace(EncodedAsmString, AsmStringsSize);
11421142
if (Insertion.second) {
11431143
// If the string is new, add it to the vector.
1144-
AsmStrings.push_back({AsmStringsSize, EncodedAsmString});
1144+
AsmStrings.emplace_back(AsmStringsSize, EncodedAsmString);
11451145
AsmStringsSize += UnescapedSize + 1;
11461146
}
11471147
unsigned AsmStrOffset = Insertion.first->second;

‎llvm/utils/TableGen/Basic/IntrinsicEmitter.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -728,7 +728,7 @@ void IntrinsicEmitter::EmitIntrinsicToBuiltinMap(
728728
// Get the map for this target prefix.
729729
auto &[Map, CommonPrefix] = BuiltinMap[Int.TargetPrefix];
730730

731-
if (!Map.insert({BuiltinName, Int.EnumName}).second)
731+
if (!Map.try_emplace(BuiltinName, Int.EnumName).second)
732732
PrintFatalError(Int.TheDef->getLoc(),
733733
"Intrinsic '" + Int.TheDef->getName() + "': duplicate " +
734734
CompilerName + " builtin name!");

‎llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -147,7 +147,7 @@ bool TypeSetByHwMode::constrain(const TypeSetByHwMode &VTS) {
147147
unsigned M = I.first;
148148
if (M == DefaultMode || hasMode(M))
149149
continue;
150-
Map.insert({M, Map.at(DefaultMode)});
150+
Map.try_emplace(M, Map.at(DefaultMode));
151151
Changed = true;
152152
}
153153
}
@@ -3297,14 +3297,14 @@ void CodeGenDAGPatterns::ParseNodeTransforms() {
32973297
reverse(Records.getAllDerivedDefinitions("SDNodeXForm"))) {
32983298
const Record *SDNode = XFormNode->getValueAsDef("Opcode");
32993299
StringRef Code = XFormNode->getValueAsString("XFormFunction");
3300-
SDNodeXForms.insert({XFormNode, NodeXForm(SDNode, Code.str())});
3300+
SDNodeXForms.try_emplace(XFormNode, NodeXForm(SDNode, Code.str()));
33013301
}
33023302
}
33033303

33043304
void CodeGenDAGPatterns::ParseComplexPatterns() {
33053305
for (const Record *R :
33063306
reverse(Records.getAllDerivedDefinitions("ComplexPattern")))
3307-
ComplexPatterns.insert({R, R});
3307+
ComplexPatterns.try_emplace(R, R);
33083308
}
33093309

33103310
/// ParsePatternFragments - Parse all of the PatFrag definitions in the .td

‎llvm/utils/TableGen/Common/CodeGenRegisters.cpp

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -466,7 +466,7 @@ void CodeGenRegister::computeSecondarySubRegs(CodeGenRegBank &RegBank) {
466466

467467
std::queue<std::pair<CodeGenSubRegIndex *, CodeGenRegister *>> SubRegQueue;
468468
for (auto [SRI, SubReg] : SubRegs)
469-
SubRegQueue.push({SRI, SubReg});
469+
SubRegQueue.emplace(SRI, SubReg);
470470

471471
// Look at the leading super-registers of each sub-register. Those are the
472472
// candidates for new sub-registers, assuming they are fully contained in
@@ -1461,7 +1461,7 @@ void CodeGenRegBank::computeComposites() {
14611461
for (const CodeGenRegister &R : Registers) {
14621462
const CodeGenRegister::SubRegMap &SM = R.getSubRegs();
14631463
for (auto [SRI, SubReg] : SM)
1464-
SubRegAction[SRI].insert({&R, SubReg});
1464+
SubRegAction[SRI].try_emplace(&R, SubReg);
14651465
}
14661466

14671467
// Calculate the composition of two subregisters as compositions of their
@@ -1474,7 +1474,7 @@ void CodeGenRegBank::computeComposites() {
14741474
for (auto [R, SubReg] : Img1) {
14751475
auto F = Img2.find(SubReg);
14761476
if (F != Img2.end())
1477-
C.insert({R, F->second});
1477+
C.try_emplace(R, F->second);
14781478
}
14791479
return C;
14801480
};

‎llvm/utils/TableGen/Common/InfoByHwMode.cpp

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -32,7 +32,7 @@ ValueTypeByHwMode::ValueTypeByHwMode(const Record *R,
3232
const CodeGenHwModes &CGH) {
3333
const HwModeSelect &MS = CGH.getHwModeSelect(R);
3434
for (const HwModeSelect::PairType &P : MS.Items) {
35-
auto I = Map.insert({P.first, MVT(llvm::getValueType(P.second))});
35+
auto I = Map.try_emplace(P.first, MVT(llvm::getValueType(P.second)));
3636
assert(I.second && "Duplicate entry?");
3737
(void)I;
3838
}
@@ -142,7 +142,7 @@ RegSizeInfoByHwMode::RegSizeInfoByHwMode(const Record *R,
142142
const CodeGenHwModes &CGH) {
143143
const HwModeSelect &MS = CGH.getHwModeSelect(R);
144144
for (const HwModeSelect::PairType &P : MS.Items) {
145-
auto I = Map.insert({P.first, RegSizeInfo(P.second)});
145+
auto I = Map.try_emplace(P.first, RegSizeInfo(P.second));
146146
assert(I.second && "Duplicate entry?");
147147
(void)I;
148148
}
@@ -195,7 +195,7 @@ SubRegRangeByHwMode::SubRegRangeByHwMode(const Record *R,
195195
const CodeGenHwModes &CGH) {
196196
const HwModeSelect &MS = CGH.getHwModeSelect(R);
197197
for (const HwModeSelect::PairType &P : MS.Items) {
198-
auto I = Map.insert({P.first, SubRegRange(P.second)});
198+
auto I = Map.try_emplace(P.first, SubRegRange(P.second));
199199
assert(I.second && "Duplicate entry?");
200200
(void)I;
201201
}
@@ -207,7 +207,7 @@ EncodingInfoByHwMode::EncodingInfoByHwMode(const Record *R,
207207
for (const HwModeSelect::PairType &P : MS.Items) {
208208
assert(P.second && P.second->isSubClassOf("InstructionEncoding") &&
209209
"Encoding must subclass InstructionEncoding");
210-
auto I = Map.insert({P.first, P.second});
210+
auto I = Map.try_emplace(P.first, P.second);
211211
assert(I.second && "Duplicate entry?");
212212
(void)I;
213213
}

‎llvm/utils/TableGen/Common/InfoByHwMode.h

Lines changed: 5 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -118,7 +118,7 @@ template <typename InfoT> struct InfoByHwMode {
118118

119119
// Copy and insert the default mode which should be first.
120120
assert(hasDefault());
121-
auto P = Map.insert({Mode, Map.begin()->second});
121+
auto P = Map.try_emplace(Mode, Map.begin()->second);
122122
return P.first->second;
123123
}
124124
const InfoT &get(unsigned Mode) const {
@@ -154,7 +154,7 @@ template <typename InfoT> struct InfoByHwMode {
154154
struct ValueTypeByHwMode : public InfoByHwMode<MVT> {
155155
ValueTypeByHwMode(const Record *R, const CodeGenHwModes &CGH);
156156
ValueTypeByHwMode(const Record *R, MVT T);
157-
ValueTypeByHwMode(MVT T) { Map.insert({DefaultMode, T}); }
157+
ValueTypeByHwMode(MVT T) { Map.try_emplace(DefaultMode, T); }
158158
ValueTypeByHwMode() = default;
159159

160160
bool operator==(const ValueTypeByHwMode &T) const;
@@ -229,7 +229,9 @@ struct SubRegRange {
229229

230230
struct SubRegRangeByHwMode : public InfoByHwMode<SubRegRange> {
231231
SubRegRangeByHwMode(const Record *R, const CodeGenHwModes &CGH);
232-
SubRegRangeByHwMode(SubRegRange Range) { Map.insert({DefaultMode, Range}); }
232+
SubRegRangeByHwMode(SubRegRange Range) {
233+
Map.try_emplace(DefaultMode, Range);
234+
}
233235
SubRegRangeByHwMode() = default;
234236

235237
void insertSubRegRangeForMode(unsigned Mode, SubRegRange Info) {

‎llvm/utils/TableGen/Common/VarLenCodeEmitterGen.cpp

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -241,21 +241,21 @@ void VarLenCodeEmitterGen::run(raw_ostream &OS) {
241241
const CodeGenHwModes &HWM = Target.getHwModes();
242242
EncodingInfoByHwMode EBM(DI->getDef(), HWM);
243243
for (const auto [Mode, EncodingDef] : EBM) {
244-
Modes.insert({Mode, "_" + HWM.getMode(Mode).Name.str()});
244+
Modes.try_emplace(Mode, "_" + HWM.getMode(Mode).Name.str());
245245
const RecordVal *RV = EncodingDef->getValue("Inst");
246246
const DagInit *DI = cast<DagInit>(RV->getValue());
247-
VarLenInsts[R].insert({Mode, VarLenInst(DI, RV)});
247+
VarLenInsts[R].try_emplace(Mode, VarLenInst(DI, RV));
248248
}
249249
continue;
250250
}
251251
}
252252
const RecordVal *RV = R->getValue("Inst");
253253
const DagInit *DI = cast<DagInit>(RV->getValue());
254-
VarLenInsts[R].insert({Universal, VarLenInst(DI, RV)});
254+
VarLenInsts[R].try_emplace(Universal, VarLenInst(DI, RV));
255255
}
256256

257257
if (Modes.empty())
258-
Modes.insert({Universal, ""}); // Base case, skip suffix.
258+
Modes.try_emplace(Universal, ""); // Base case, skip suffix.
259259

260260
// Emit function declaration
261261
OS << "void " << Target.getName()

‎llvm/utils/TableGen/CompressInstEmitter.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -541,9 +541,9 @@ getReqFeatures(std::set<std::pair<bool, StringRef>> &FeaturesSet,
541541
!cast<DefInit>(Arg)->getDef()->isSubClassOf("SubtargetFeature"))
542542
PrintFatalError(R->getLoc(), "Invalid AssemblerCondDag!");
543543
if (IsOr)
544-
AnyOfSet.insert({IsNot, cast<DefInit>(Arg)->getDef()->getName()});
544+
AnyOfSet.emplace(IsNot, cast<DefInit>(Arg)->getDef()->getName());
545545
else
546-
FeaturesSet.insert({IsNot, cast<DefInit>(Arg)->getDef()->getName()});
546+
FeaturesSet.emplace(IsNot, cast<DefInit>(Arg)->getDef()->getName());
547547
}
548548

549549
if (IsOr)

‎llvm/utils/TableGen/DAGISelMatcherEmitter.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -151,7 +151,7 @@ class MatcherTableEmitter {
151151
Uses += PredicateUsage[TP];
152152

153153
// We only add the first predicate here since they are with the same code.
154-
PredicateList.push_back({TPs[0], Uses});
154+
PredicateList.emplace_back(TPs[0], Uses);
155155
}
156156

157157
stable_sort(PredicateList, [](const auto &A, const auto &B) {

‎llvm/utils/TableGen/InstrInfoEmitter.cpp

Lines changed: 4 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -203,7 +203,7 @@ InstrInfoEmitter::CollectOperandInfo(OperandInfoListTy &OperandInfoList,
203203
unsigned Offset = 0;
204204
for (const CodeGenInstruction *Inst : Target.getInstructionsByEnumValue()) {
205205
OperandInfoTy OperandInfo = GetOperandInfo(*Inst);
206-
if (OperandInfoMap.insert({OperandInfo, Offset}).second) {
206+
if (OperandInfoMap.try_emplace(OperandInfo, Offset).second) {
207207
OperandInfoList.push_back(OperandInfo);
208208
Offset += OperandInfo.size();
209209
}
@@ -503,7 +503,8 @@ void InstrInfoEmitter::emitLogicalOperandSizeMappings(
503503
LogicalOpListSize = std::max(LogicalOpList.size(), LogicalOpListSize);
504504

505505
auto I =
506-
LogicalOpSizeMap.insert({LogicalOpList, LogicalOpSizeMap.size()}).first;
506+
LogicalOpSizeMap.try_emplace(LogicalOpList, LogicalOpSizeMap.size())
507+
.first;
507508
InstMap[I->second].push_back(
508509
(Namespace + "::" + Inst->TheDef->getName()).str());
509510
}
@@ -850,7 +851,7 @@ void InstrInfoEmitter::run(raw_ostream &OS) {
850851

851852
std::vector<const Record *> ImplicitOps = Inst->ImplicitUses;
852853
llvm::append_range(ImplicitOps, Inst->ImplicitDefs);
853-
if (EmittedLists.insert({ImplicitOps, ImplicitListSize}).second) {
854+
if (EmittedLists.try_emplace(ImplicitOps, ImplicitListSize).second) {
854855
ImplicitLists.push_back(ImplicitOps);
855856
ImplicitListSize += ImplicitOps.size();
856857
}

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