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[RISCV] Add TT-Ascalon-d8 processor (#115100)
Ascalon is an out-of-order CPU core from Tenstorrent. Overview: https://tenstorrent.com/ip/tt-ascalon Adding 8-wide version, -mcpu=tt-ascalon-d8. Scheduling model will be added in a separate PR. --------- Co-authored-by: Anton Blanchard <antonb@tenstorrent.com>
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‎clang/test/Driver/riscv-cpus.c

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// RUN: %clang --target=riscv32 -### -c %s 2>&1 -mtune=syntacore-scr1-max | FileCheck -check-prefix=MTUNE-SYNTACORE-SCR1-MAX %s
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// MTUNE-SYNTACORE-SCR1-MAX: "-tune-cpu" "syntacore-scr1-max"
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// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mtune=tt-ascalon-d8 | FileCheck -check-prefix=MTUNE-TT-ASCALON-D8 %s
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// MTUNE-TT-ASCALON-D8: "-tune-cpu" "tt-ascalon-d8"
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// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=tt-ascalon-d8 | FileCheck -check-prefix=MCPU-TT-ASCALON-D8 %s
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// MCPU-TT-ASCALON-D8: "-target-cpu" "tt-ascalon-d8"
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// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+m"
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// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+a"
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// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+f"
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// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+d"
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// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+c"
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// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+v"
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// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+h"
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// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zicbom"
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// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zicbop"
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// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zicboz"
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// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zicntr"
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// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zicond"
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// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zicsr"
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// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zifencei"
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// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zihintntl"
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// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zihintpause"
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// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zihpm"
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// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zimop"
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// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zmmul"
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// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zawrs"
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// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zfa"
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// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zfbfmin"
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// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zfh"
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// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zfhmin"
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// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zca"
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// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zcb"
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// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zba"
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// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zbb"
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// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zbs"
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// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zkt"
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// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zvbb"
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// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zvbc"
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// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zve32f"
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// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zve32x"
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// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zve64d"
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// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zve64f"
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// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zve64x"
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// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zvfbfmin"
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// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zvfbfwma"
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// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zvfh"
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// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zvfhmin"
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// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zvkb"
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// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zvkg"
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// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zvkn"
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// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zvknc"
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// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zvkned"
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// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zvkng"
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// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zvknhb"
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// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zvkt"
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// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zvl128b"
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// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zvl256b"
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// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zvl32b"
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// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zvl64b"
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// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+svinval"
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// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+svnapot"
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// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+svpbmt"
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// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=veyron-v1 | FileCheck -check-prefix=MCPU-VEYRON-V1 %s
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// MCPU-VEYRON-V1: "-target-cpu" "veyron-v1"
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// MCPU-VEYRON-V1: "-target-feature" "+m"

‎clang/test/Misc/target-invalid-cpu-note/riscv.c

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// RISCV64-SAME: {{^}}, syntacore-scr4-rv64
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// RISCV64-SAME: {{^}}, syntacore-scr5-rv64
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// RISCV64-SAME: {{^}}, syntacore-scr7
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// RISCV64-SAME: {{^}}, tt-ascalon-d8
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// RISCV64-SAME: {{^}}, veyron-v1
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// RISCV64-SAME: {{^}}, xiangshan-nanhu
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// RISCV64-SAME: {{$}}
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// TUNE-RISCV64-SAME: {{^}}, syntacore-scr4-rv64
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// TUNE-RISCV64-SAME: {{^}}, syntacore-scr5-rv64
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// TUNE-RISCV64-SAME: {{^}}, syntacore-scr7
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// TUNE-RISCV64-SAME: {{^}}, tt-ascalon-d8
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// TUNE-RISCV64-SAME: {{^}}, veyron-v1
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// TUNE-RISCV64-SAME: {{^}}, xiangshan-nanhu
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// TUNE-RISCV64-SAME: {{^}}, generic

‎llvm/docs/ReleaseNotes.md

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* The `Zvbc32e` and `Zvkgs` extensions are now supported experimentally.
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* Added `Smctr`, `Ssctr` and `Svvptc` extensions.
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* `-mcpu=syntacore-scr7` was added.
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* `-mcpu=tt-ascalon-d8` was added.
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* The `Zacas` extension is no longer marked as experimental.
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* Added Smdbltrp, Ssdbltrp extensions to -march.
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* The `Smmpm`, `Smnpm`, `Ssnpm`, `Supm`, and `Sspm` pointer masking extensions

‎llvm/lib/Target/RISCV/RISCVProcessors.td

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FeatureStdExtZkn],
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[TuneNoDefaultUnroll, FeaturePostRAScheduler]>;
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def TENSTORRENT_ASCALON_D8 : RISCVProcessorModel<"tt-ascalon-d8",
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NoSchedModel,
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!listconcat(RVA23S64Features,
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[FeatureStdExtSmaia,
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FeatureStdExtSsaia,
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FeatureStdExtSscofpmf,
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FeatureStdExtSsstrict,
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FeatureStdExtZfbfmin,
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FeatureStdExtZfh,
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FeatureStdExtZicsr,
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FeatureStdExtZvbc,
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FeatureStdExtZvfbfmin,
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FeatureStdExtZvfbfwma,
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FeatureStdExtZvfh,
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FeatureStdExtZvkng,
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FeatureStdExtZvl256b,
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FeatureUnalignedScalarMem,
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FeatureUnalignedVectorMem]),
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[TuneNoDefaultUnroll,
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TuneOptimizedZeroStrideLoad,
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FeaturePostRAScheduler]>;
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def VENTANA_VEYRON_V1 : RISCVProcessorModel<"veyron-v1",
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NoSchedModel,
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[Feature64Bit,

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